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AD9204-20EBZ1 Arkusz danych(PDF) 7 Page - Analog Devices

Numer części AD9204-20EBZ1
Szczegółowy opis  10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
Download  36 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9204-20EBZ1 Arkusz danych(HTML) 7 Page - Analog Devices

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AD9204
Rev. 0 | Page 7 of 36
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 4.
Parameter
Temp
AD9204-20/AD9204-40
AD9204-65
AD9204-80
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
625
625
625
MHz
Conversion Rate1
Full
3
20/40
3
65
3
80
MSPS
CLK Period—Divide-by-1 Mode (tCLK)
Full
50/25
15.38
12.5
ns
CLK Pulse Width High (tCH)
25.0/12.5
7.69
6.25
ns
Aperture Delay (tA)
Full
1.0
1.0
1.0
ns
Aperture Uncertainty (Jitter, tJ)
Full
0.1
0.1
0.1
ps rms
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
Full
3
3
3
ns
DCO Propagation Delay (tDCO)
Full
3
3
3
ns
DCO to Data Skew (tSKEW)
Full
0.1
0.1
0.1
ns
Pipeline Delay (Latency)
Full
9
9
9
Cycles
Wake-Up Time2
Full
350
350
350
μs
Standby
Full
600/400
300
260
ns
OUT-OF-RANGE RECOVERY TIME
Full
2
2
2
Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
tPD
tSKEW
tCH
tDCO
tCLK
N – 9
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
N – 8N – 7N – 6N – 5
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
Figure 2. CMOS Output Data Timing
tPD
tSKEW
tCH
tDCO
tCLK
CH A
N – 9
CH B
N – 9
CH A
N – 8
CH B
N – 8
CH A
N – 7
CH B
N – 7
CH A
N – 6
CH B
N – 6
CH A
N – 5
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A/CH B DATA
DCOA/DCOB
tA
Figure 3. CMOS Interleaved Output Timing


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