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FM24C256FLZEYYX Arkusz danych(PDF) 5 Page - Fairchild Semiconductor |
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FM24C256FLZEYYX Arkusz danych(HTML) 5 Page - Fairchild Semiconductor |
5 / 12 page 5 www.fairchildsemi.com FM24C256 rev. B.3 AC Conditions of Test Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10 ns Input & Output Timing Levels VCC x 0.5 Output Load 1 TTL Gate and C L = 100 pF Read and Write Cycle Limits (Standard and Low V CC Range - 2.7V-5.5V) Symbol Parameter 100 kHz 400 kHz Units Min Max Min Max fSCL SCL Clock Frequency 100 400 kHz T I Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN 100 50 ns Pulse width) tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.3 1.2 µs t BUF Time the Bus Must Be Free before 4.7 1.3 µs a New Transmission Can Start t HD:STA Start Condition Hold Time 4.0 0.6 µs t LOW Clock Low Period 4.7 1.5 µs tHIGH Clock High Period 4.0 0.6 µs t SU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) t HD:DAT Data in Hold Time 0 0 µs t SU:DAT Data in Setup Time 250 100 ns tR SDA and SCL Rise Time 1 0.3 µs t F SDA and SCL Fall Time 300 300 ns t SU:STO Stop Condition Setup Time 4.7 0.6 µs tDH Data Out Hold Time 100 100 ns t WR Write Cycle Time 6 6 ms (Note 2) Note 2: The write cycle time (t WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address |
Podobny numer części - FM24C256FLZEYYX |
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Podobny opis - FM24C256FLZEYYX |
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