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TMP175AIDGKT Arkusz danych(PDF) 7 Page - Texas Instruments |
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TMP175AIDGKT Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 20 page TMP175 TMP75 SBOS288J − JANUARY 2004 − REVISED DECEMBER 2007 www.ti.com 7 resolution or faster conversion time. Table 8 identifies the Resolution Bits and the relationship between resolution and conversion time. R1 R0 RESOLUTION CONVERSION TIME (typical) 0 0 9 Bits (0.5 °C) 27.5ms 0 1 10 Bits (0.25 °C) 55ms 1 0 11 Bits (0.125 °C) 110ms 1 1 12 Bits (0.0625 °C) 220ms Table 8. Resolution of the TMP175 and TMP75 ONE-SHOT (OS) The TMP175 and TMP75 feature a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode, writing a ‘1’ to the OS bit will start a single temperature conversion. The device will return to the shutdown state at the completion of the single conversion. This is useful to reduce power consumption in the TMP175 and TMP75 when continuous temperature monitoring is not required. When the configuration register is read, the OS will always read zero. HIGH AND LOW LIMIT REGISTERS In Comparator Mode (TM = 0), the ALERT pin of the TMP175 and TMP75 becomes active when the temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin will remain active until the temperature falls below the indicated TLOW value for the same number of faults. In Interrupt Mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs, or the device successfully responds to the SMBus Alert Response Address. The ALERT pin will also be cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active again by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin will become active and remain active until cleared by a read operation of any register or a successful response to the SMBus Alert Response Address. Once the ALERT pin is cleared, the above cycle will repeat, with the ALERT pin becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General Call Reset command. This will also clear the state of the internal registers in the device returning the device to Comparator Mode (TM = 0). Both operational modes are represented in Figure 3. Table 9 and Table 10 describe the format for the THIGH and TLOW registers. Note that the most significant byte is sent first, followed by the least significant byte. Power-up reset values for THIGH and TLOW are: THIGH = 80°C and TLOW = 75°C The format of the data for THIGH and TLOW is the same as for the Temperature Register. BYTE D7 D6 D5 D4 D3 D2 D1 D0 1 H11 H10 H9 H8 H7 H6 H5 H4 BYTE D7 D6 D5 D4 D3 D2 D1 D0 2 H3 H2 H1 H0 0 0 0 0 Table 9. Bytes 1 and 2 of THIGH Register BYTE D7 D6 D5 D4 D3 D2 D1 D0 1 L11 L10 L9 L8 L7 L6 L5 L4 BYTE D7 D6 D5 D4 D3 D2 D1 D0 2 L3 L2 L1 L0 0 0 0 0 Table 10. Bytes 1 and 2 of TLOW Register All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is configured for 9-bit resolution. SERIAL INTERFACE The TMP175 and TMP75 operate only as slave devices on the Two-Wire bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP175 and TMP75 both support the transmission protocol for fast (1kHz to 400kHz) and high-speed (1kHz to 3.4MHz) modes. All data bytes are transmitted MSB first. SERIAL BUS ADDRESS To communicate with the TMP175 and TMP75, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. |
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