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AD5306BRUZ-REEL1 Arkusz danych(PDF) 8 Page - Analog Devices |
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AD5306BRUZ-REEL1 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 24 page AD5306/AD5316/AD5326 Rev. F | Page 8 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VOUTA VOUTB VREFB VREFA VOUTC LDAC A0 SCL SDA PD VREFCVREFD VOUTD GND A1 AD5306/ AD5316/ AD5326 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. 2 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled with a10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 3 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 4 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 5 VOUTC Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 6 VREFA Reference Input Pin for DAC A. This pin can be configured as a buffered or an unbuffered input depending on the state of the BUF bit in the input word to DAC A. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 7 VREFB Reference Input Pin for DAC B. This pin can be configured as a buffered or an unbuffered input depending on the state of the BUF bit in the input word to DAC B. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 8 VREFC Reference Input Pin for DAC C. This pin can be configured as a buffered or an unbuffered input depending on the state of the BUF bit in the input word to DAC C. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 9 VREFD Reference Input Pin for DAC D. This pin can be configured as a buffered or an unbuffered input depending on the state of the BUF bit in the input word to DAC D. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 10 PD Active Low Control Input. Acts as a hardware power-down option. All DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state. The current consumption of the part drops to 300 nA @ 5 V (90 nA @ 3 V). 11 VOUTD Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 12 GND Ground Reference Point for All Circuitry on the Part. 13 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 14 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift register. Clock rates of up to 400 kbps can be accommodated in the I2C-compatible interface. 15 A0 Address Input. Sets the LSB of the 7-bit slave address. 16 A1 Address Input. Sets the second LSB of the 7-bit slave address. |
Podobny numer części - AD5306BRUZ-REEL1 |
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Podobny opis - AD5306BRUZ-REEL1 |
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