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AD5360BCPZ1 Arkusz danych(PDF) 1 Page - Analog Devices |
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AD5360BCPZ1 Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 28 page 16-Channel, 16-/14-Bit, Serial Input, Voltage-Output DAC AD5360/AD5361 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved. FEATURES 16-channel DAC in 52-lead LQFP and 56-lead LFCSP packages Guaranteed monotonic to 16/14 bits Nominal output voltage range of −10 V to +10 V Multiple output spans available Temperature monitoring function Channel monitoring multiplexer GPIO function System calibration function allowing user-programmable offset and gain Channel grouping and addressing features Data error checking feature SPI-compatible serial interface 2.5 V to 5.5 V digital interface Digital reset (RESET) Clear function to user-defined SIGGNDx Simultaneous update of DAC outputs APPLICATIONS Instrumentation Industrial control systems Level setting in automatic test equipment (ATE) Variable optical attenuators (VOA) Optical line cards FUNCTIONAL BLOCK DIAGRAM n SERIAL INTERFACE 8 6 n n 8 8 14 n n n ·· ·· · ·· ·· ·· ·· ·· ·· ·· ·· ·· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · n 8 8 14 14 ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· ·· · · · · · · · · · · · · · · · · · · · · · · · · · · · · n n n n n n n n SDI SCLK SDO SYNC BUSY RESET CLR STATE MACHINE CONTROL REGISTER GPIO REGISTER GPIO MON_OUT MON_IN1 MON_IN0 PEC TEMP_OUT BIN/2SCOMP TEMP SENSOR AD5360/ AD5361 A/B SELECT REGISTER n = 16 FOR AD5360 n = 14 FOR AD5361 · A/B SELECT REGISTER X1 REGISTER M REGISTER C REGISTER TO MUX 2s TO MUX 2s A/B MUX MUX 2 DAC 7 REGISTER DAC 0 REGISTER OFS1 REGISTER DAC 0 REGISTER OFS0 REGISTER DAC 7 REGISTER X2A REGISTER X2B REGISTER OFFSET DAC 0 DAC 0 DAC 7 OFFSET DAC 1 DAC 0 DAC 7 BUFFER BUFFER BUFFER GROUP 0 GROUP 1 OUTPUT BUFFER AND POWER- DOWN CONTROL OUTPUT BUFFER AND POWER- DOWN CONTROL OUTPUT BUFFER AND POWER- DOWN CONTROL OUTPUT BUFFER AND POWER- DOWN CONTROL VREF0 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13 VOUT14 VOUT15 VOUT7 SIGGND0 SIGGND1 VREF1 n n n n n n n X1 REGISTER M REGISTER C REGISTER A/B MUX MUX 2 X2A REGISTER X2B REGISTER DVCC VDD VSS AGND DGND LDAC n n n n n n n n X1 REGISTER M REGISTER C REGISTER A/B MUX MUX 2 X2A REGISTER X2B REGISTER n n n n 2 n n n n X1 REGISTER M REGISTER C REGISTER A/B MUX MUX 2 X2A REGISTER X2B REGISTER MUX VOUT0 TO VOUT15 Figure 1. |
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