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ADXL375 Arkusz danych(PDF) 11 Page - Analog Devices |
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ADXL375 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 32 page Data Sheet ADXL375 Rev. 0 | Page 11 of 32 POWER SAVING MODES Low Power Mode A low power mode is available for additional power savings. In low power mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 Hz to 400 Hz data rate range at the expense of slightly greater noise. To enter low power mode, set the LOW_POWER bit (Bit D4) in the BW_RATE register (Address 0x2C). Table 8 shows the current consumption in low power mode for output data rates where there is an advantage to using low power mode. Table 8. Typical Current Consumption vs. Data Rate, Low Power Mode (TA = 25°C, VS = 2.5 V, VDDI/O = 1.8 V) Rate Bits Output Data Rate (Hz) Bandwidth (Hz) IDD (µA) 1100 400 200 90 1011 200 100 60 1010 100 50 50 1001 50 25 45 1000 25 12.5 40 0111 12.5 6.25 35 For data rates not shown in Table 8, the use of low power mode does not provide any advantage over normal power mode. There- fore, it is recommended that low power mode be used only for the data rates shown in Table 8. Autosleep Mode Additional power can be saved if the ADXL375 automatically switches to sleep mode during periods of inactivity. To enable the autosleep mode feature, 1. Set the THRESH_INACT register (Address 0x25) and the TIME_INACT register (Address 0x26) to values that signify inactivity. The appropriate values depend on the application. 2. Set the AUTO_SLEEP bit (Bit D4) and the link bit (Bit D5) in the POWER_CTL register (Address 0x2D). Current consumption at the sub-12.5 Hz data rates that are used in autosleep mode is typically 35 µA for VS = 2.5 V. For information about the advantages of using low power mode vs. autosleep mode, see the Sleep Mode vs. Low Power Mode section. Standby Mode For even lower power operation, standby mode can be used. In standby mode, current consumption is reduced to 0.1 µA (typical). In this mode, no measurements are made, but the contents of the FIFO buffer are preserved. To enter standby mode, clear the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D). FIFO BUFFER The ADXL375 contains patented technology for an embedded memory management system with a 32-level FIFO buffer that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger. Each mode can be selected by setting the FIFO_MODE bits (Bits[D7:D6]) in the FIFO_CTL register (Address 0x38; see Table 9). Table 9. FIFO Modes (FIFO_CTL Register, Address 0x38) Setting FIFO Mode D7 D6 Description 0 0 Bypass FIFO buffer is bypassed. 0 1 FIFO FIFO buffer collects up to 32 samples and then stops collecting data, collecting new data only when the buffer is not full. 1 0 Stream FIFO buffer holds the last 32 samples. When the buffer is full, the oldest data is overwritten with newer data. 1 1 Trigger FIFO buffer holds the last samples before the trigger event and continues to collect data until full. New data is collected only when the buffer is not full. For an in-depth description of the FIFO buffer and FIFO modes, see the AN-1025 Application Note, Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc., Digital Accelerometers. Bypass Mode In bypass mode, the FIFO buffer is not operational and, there- fore, remains empty. FIFO Mode In FIFO mode, data from measurements of the x-, y-, and z-axes is stored in the FIFO buffer. When the number of samples in the FIFO buffer equals the level specified by the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set (see the Watermark Bit section). The FIFO buffer continues to accumulate samples until it is full (32 samples from measure- ments of the x-, y-, and z-axes) and then stops collecting data. After the FIFO buffer stops collecting data, the device continues to operate; therefore, features such as shock detection can be used after the FIFO buffer is full. The watermark interrupt bit remains set until the number of samples in the FIFO buffer is less than the value stored in the samples bits of the FIFO_CTL register. Stream Mode In stream mode, data from measurements of the x-, y-, and z-axes is stored in the FIFO buffer. When the number of samples in the FIFO buffer equals the level specified by the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set (see the Watermark Bit section). The FIFO buffer continues to accumulate samples; the buffer stores the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new data arrives. The watermark interrupt bit remains set until the number of samples in the FIFO buffer is less than the value stored in the samples bits of the FIFO_CTL register. |
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