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FW21154AE Arkusz danych(PDF) 5 Page - Intel Corporation |
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FW21154AE Arkusz danych(HTML) 5 Page - Intel Corporation |
5 / 36 page 21154 PCI-to-PCI Bridge Specification Update Intel Confidential5 Revision History Date Version Description July 2004 017 Updated Errata 9. description. 2/25/05 016 The following changes have been made in this version: • Updated status for Errata 7. and Errata 9. on page 11. • Revised Pin 1 Designator Change description in “Specification Changes” on page 11. • Added Errata 10. “Secondary Address pins are driven incorrectly during reset.” on page 21. • Added documentation change “Updated Version of PCI Local Bus Specification” on page 36. 3/1/02 015 The following changes have been made in this Specification Update: • Updated Errata table status column on page 11. Updated status for Erratas 1 through 6. • Added Recommendation #1 fix for Errata 6 “Secondary Clocks Outputs s_clk_o<9:0> May Not Start-up Properly Under Some Conditions”. Moved previously existing fix recommendation for Errata 6 to become the second recommendation. • Added Errata 9, “21154AE/BE May Experience Performance Problems or Hangs when P_VIO = 3.3V” on page 20. • Updated Specification Clarification 1 title description on page 23. • Updated links in this document. 6/25/01 014 Updated Errata #1 description in Table , “Errata” on page 11 and added new worst-case conditions tables for Tval description,Section 1 on page 15 6/8/01 013 Updated Errata #1 title description in Table , “Errata” on page 11 and added worst-case conditions for Tval description,Section 1 on page 15 |
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