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UC1843TD2 Arkusz danych(PDF) 2 Page - Texas Instruments |
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UC1843TD2 Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 4 page a b c d Origin UC1843-DIE SLUSBN6 – JULY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. BARE DIE INFORMATION BACKSIDE BOND PAD BOND PAD DIE THICKNESS BACKSIDE FINISH POTENTIAL METALLIZATION COMPOSITION THICKNESS 10.5 mils. Silicon with backgrind Floating AlCu2% 2000 nm Table 1. BOND PAD COORDINATES (in Mils) DESCRIPTION PAD NUMBER a b c d COMP 1 78.70 63.40 82.90 67.60 VFB 2 70.60 63.40 74.80 67.60 ISENSE 3 39.40 63.40 43.60 67.60 RT/CT 4 18.60 61.20 22.60 65.60 GROUND 5 17.80 11.70 22.00 15.90 GROUND 6 17.40 3.90 21.80 8.10 OUTPUT 7 32.60 6.40 36.80 10.60 VCC 8 47.50 6.40 51.70 10.60 VCC 9 54.60 6.40 58.80 10.60 VREF 10 68.70 6.40 72.90 10.60 NC TESTPAD 87.10 6.30 90.80 10.30 NC TESTPAD 87.10 12.60 90.80 16.60 NC TESTPAD 87.10 18.00 90.80 22.00 NC TESTPAD 87.10 24.30 90.80 28.30 NC TESTPAD 87.10 30.60 90.80 34.60 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: UC1843-DIE |
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