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ADRF6703 Arkusz danych(PDF) 9 Page - Analog Devices |
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ADRF6703 Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 36 page Data Sheet ADRF6702 Rev. B | Page 9 of 36 Pin No. Mnemonic Description 13 CLK Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. 14 LE Latch Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. 16 ENOP Modulator Output Enable/Disable. See Table 6. 18, 19, 32, 33 QP, QN, IN, IP Modulator Baseband Inputs. Differential in-phase and quadrature baseband inputs. These inputs should be dc-biased to 0.5 V. 26 RFOUT RF Output. Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled to its load. 36 LOSEL LO Select. This digital input pin determines whether the LOP and LON pins operate as inputs or outputs. This pin should not be left floating. LOP and LON become inputs if the LOSEL pin is set low and the LDRV bit of Register 5 is set low. External LO drive must be a 2× LO. In addition to setting LOSEL and LDRV low and providing an external 2× LO, the LXL bit of Register 5 (DB4) must be set to 1 to direct the external LO to the IQ modulator. LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set to 1. A 1× LO or 2× LO output can be selected by setting the LDIV bit of Register 5 (DB5) to 1 or 0 respectively (see Table 7). 37, 38 LON, LOP Local Oscillator Input/Output. The internally generated 1× LO or 2× LO is available on these pins. When internal LO generation is disabled, an external 1× LO or 2× LO can be applied to these pins. 39 VTUNE VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.3 V to 2.5 V. If the external VCO mode is activated, this pin can be left open. 40 DECL3 Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground. EP Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane. Table 6. Enabling RFOUT ENOP Register 5 Bit DB6 RFOUT X1 0 Disabled 0 X1 Disabled 1 1 Enabled 1 X = don’t care. Table 7. LO Port Configuration1, 2 LON/LOP Function LOSEL Register 5 Bit DB5(LDIV) Register 5 Bit DB4(LXL) Register 5 Bit DB3 (LDRV) Input (2× LO) 0 X 1 0 Output (Disabled) 0 X 0 0 Output (1× LO) 0 0 0 1 Output (1× LO) 1 0 0 0 Output (1× LO) 1 0 0 1 Output (2× LO) 0 1 0 1 Output (2× LO) 1 1 0 0 Output (2× LO) 1 1 0 1 1 X = don’t care. 2 LOSEL should not be left floating. |
Podobny numer części - ADRF6703 |
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Podobny opis - ADRF6703 |
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