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ML4821 Arkusz danych(PDF) 2 Page - Fairchild Semiconductor |
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ML4821 Arkusz danych(HTML) 2 Page - Fairchild Semiconductor |
2 / 12 page ML4821 PRODUCT SPECIFICATION 2 REV. 1.0.2 6/19/01 Pin Connection Pin Description Pin Number Name Function 18-Pin DIP 20-Pin SOIC 11 ILIM Peak cycle-by-cycle current limit input 2 2 IA OUT Output and compensation node of the average current error amplifier 33 IA– Inverting input of the average current error amplifier 4 4 IA+ Non-Inverting input of the average current error amplifier and output of the gain modulator 55 ISINE Gain modulator input 6 6 EA OUT Output of output voltage error amplifier 7 7 INV Inverting input to error amplifier 88 VRMS Input for average line voltage compensation 9 9 SOFT START Normally connected to soft start capacitor 10 12 SYNC Oscillator synchronization input 11 13 OVP Inhibits output pulses when the voltage at this pin exceeds 5V. Also, when the voltage at this pin is less than 0.7V, the IC goes into low current shut-down mode. 12 14 RT Timing resistor for the oscillator 13 15 PWR GND Return for the high current totem pole output 14 16 OUT High current totem pole output 15 17 VCC Positive supply for the IC 16 18 VREF Buffered output for the 5V voltage reference 17 19 CT Timing capacitor for the oscillator. 18 20 GND Analog signal ground ILIM IA OUT IA– IA+ ISINE EA OUT EA– VRMS SOFT START GND CT VREF VCC OUT PGND RT OVP SYNC ILIM IA OUT IA– IA+ ISINE EA OUT EA– VRMS SOFT START N/C GND CT VREF VCC OUT PGND RT OVP SYNC N/C 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 TOP VIEW 18-Pin PDIP (P18) 20-Pin SOIC (S20) TOP VIEW |
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