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AD9201-EVAL Arkusz danych(PDF) 4 Page - Analog Devices |
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AD9201-EVAL Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 4 page AD9201 –4– REV. D CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS* With Respect Parameter to Min Max Units AVDD AVSS –0.3 +6.5 V DVDD DVSS –0.3 +6.5 V AVSS DVSS –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V AINA, AINB AVSS –1.0 AVDD + 0.3 V VREF AVSS –0.3 AVDD + 0.3 V REFSENSE AVSS –0.3 AVDD + 0.3 V REFT, REFB AVSS –0.3 AVDD + 0.3 V Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature 10 sec +300 °C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Options* AD9201ARS –40 °C to +85°C 28-Lead SSOP RS-28 AD9201-EVAL Evaluation Board *RS = Shrink Small Outline. PIN CONFIGURATION TOP VIEW (Not to Scale) AD9201 REFT-Q INB-Q INA-Q CHIP-SELECT VREF AVDD REFB-Q REFB-I AVSS REFSENSE REFT-I SLEEP INA-I INB-I DVSS DVDD (LSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 (MSB) D9 SELECT CLOCK PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 DVSS Digital Ground 2 DVDD Digital Supply 3 D0 Bit 0 (LSB) 4 D1 Bit 1 5 D2 Bit 2 6 D3 Bit 3 7 D4 Bit 4 8 D5 Bit 5 9 D6 Bit 6 10 D7 Bit 7 11 D8 Bit 8 12 D9 Bit 9 (MSB) 13 SELECT Hi I Channel Out, Lo Q Channel Out 14 CLOCK Clock 15 SLEEP Hi Power Down, Lo Normal Operation 16 INA-I I Channel, A Input 17 INB-I I Channel, B Input 18 REFT-I Top Reference Decoupling, I Channel 19 REFB-I Bottom Reference Decoupling, I Channel 20 AVSS Analog Ground 21 REFSENSE Reference Select 22 VREF Internal Reference Output 23 AVDD Analog Supply 24 REFB-Q Bottom Reference Decoupling, Q Channel 25 REFT-Q Top Reference Decoupling, Q Channel 26 INB-Q Q Channel, B Input 27 INA-Q Q Channel, A Input 28 CHIP-SELECT Hi-High Impedance, Lo-Normal Operation WARNING! ESD SENSITIVE DEVICE DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB before the first code tran- sition. “Full scale” is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed. |
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