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AD9059BRS Arkusz danych(PDF) 7 Page - Analog Devices |
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AD9059BRS Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 12 page REV. A AD9059 –7– THEORY OF OPERATION The AD9059 combines Analog Devices’ proprietary MagAmp gray code conversion circuitry with flash converter technology to provide dual high performance 8-bit ADCs in a single low cost monolithic device. The design architecture ensures low power, high speed, and 8-bit accuracy. The AD9059 provides two linked ADC channels that are clocked from a single ENCODE input (see Functional Block Diagram). The two ADC channels simultaneously sample the analog inputs (AINA and AINB) and provide noninterleaved parallel digital outputs (D0A–D7A and D0B–D7B). The voltage reference (VREF) is internally connected to both ADCs so channel gains and offsets will track if external reference control is desired. The analog input signal is buffered at the input of each ADC channel and applied to a high speed track-and-hold. The track- and-hold circuit holds the analog input value during the conversion process (beginning with the rising edge of the ENCODE command). The track-and-hold’s output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input level. Decode logic combines the multistage data and aligns the 8-bit word for strobed outputs on the rising edge of the ENCODE command. The MagAmp/Flash architecture of the AD9059 results in three pipeline delays for the output data. USING THE AD9059 Analog Inputs The AD9059 provides independent single-ended high impedance (150 k Ω) analog inputs for the dual ADCs. Each input requires a dc bias current of 6 µA (typical) centered near 2.5 V (±10%). The dc bias may be provided by the user or may be derived from the ADC’s internal voltage reference. Figure 2 shows a low cost dc bias implementation that allows the user to capacitively couple ac signals directly into the ADC without additional active cir- cuitry. For best dynamic performance, the VREF pin should be decoupled to ground with a 0.1 µF capacitor (to minimize modulation of the reference voltage), and the bias resistor should be approximately 1 k Ω. 1 3 1k 1k AINA AINB VREF AD9059 0.1µF 0.1µF 0.1µF 5V VINA (1V p-p) EXTERNAL VREF (OPTIONAL) VINB (1V p-p) 28 Figure 2. Capacity Coupled AD9059 Figure 3 shows typical connections for high performance dc biasing using the ADC’s internal voltage reference. All compo- nents may be powered from a single 5 V supply (analog input signals are referenced to ground). 28 1 10k 1k AINA AINB VREF AD9059 0.1µF +5V VINA VIN B (–0.5V TO +0.5V) 10k +5V 5V AD8041 AD8041 1k 1k 1k 3 Figure 3. DC-Coupled AD9059 (VIN Inverted) Voltage Reference A stable and accurate 2.5 V voltage reference is built into the AD9059 (VREF). The reference output is used to set the ADC gain/offset and can provide dc bias for the analog input signals. The internal reference is tied to the ADC circuitry through an 800 Ω internal impedance and is capable of providing 300 µA external drive current (for dc biasing the analog input or other user circuitry). Some applications may require greater accuracy, improved temperature performance, or gain adjustments that cannot be obtained using the internal reference. An external voltage may be applied to the VREF pin to overdrive the internal voltage reference for gain adjustment of up to ±10% (the VREF pin is internally tied directly to the ADC circuitry). ADC gain and offset will vary simultaneously with external reference adjust- ment with a 1:1 ratio (a 2% or 50 mV adjustment to the 2.5 V reference varies ADC gain by 2% and ADC offset by 50 mV). Theoretical input voltage range versus reference input voltage may be calculated using the following equations. Vp p VREF V VREF V VREF V V VREF V RANGE MIDSCALE TOP OF RANGE RANGE BOTTOM OF RANGE RANGE () . – −= = =+ = −− −− 25 2 2 The external reference should have a 1 mA minimum sink/ source current capability to ensure complete overdrive of the internal voltage reference. |
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