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AD724JR-REEL Arkusz danych(PDF) 9 Page - Analog Devices |
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AD724JR-REEL Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 15 page AD724 REV. B –9– The filtered chrominance signal is then summed with the fil- tered luminance signal to create the composite video signal. The separate luminance, chrominance and composite video voltages are amplified by two in order to drive 75 Ω reverse-terminated lines. The separate luminance and chrominance outputs to- gether are known as S-video. The composite and S-video out- puts are simultaneously available. The two sync inputs HSYNC and VSYNC drive an XNOR gate to create a CSYNC signal for the AD724. If the user produces a true composite sync signal, it can be input to the HSYNC pin while the VSYNC pin is held high. In either case the CSYNC signal that is present after the XNOR gate is used to generate the sync and burst signals that are injected into the analog signal chain. The unclocked CSYNC signal is sent to a reference cell on the chip which, when CSYNC is low, allows a reference voltage to be injected into the luminance chain. The width of the injected sync is the same as the width of the supplied sync signal. The CSYNC signal (after the XNOR gate) is also routed to the digital section of the AD724 where it is clocked in by a 2FSC clock. The digital circuitry then measures the width of the CSYNC pulses to separate horizontal pulses from equalization and serration pulses. A burst flag is generated only after valid horizontal sync pulses, and drives a reference cell to inject the proper voltages into the U and V low-pass filters. This burst flag is timed from the falling edge of the clocked-in CSYNC signal. In synchronous systems (systems in which the subcarrier clock, sync signals, and RGB signals are all synchronous) this will give a fixed burst position relative to the falling edge of the output sync. However, in asynchronous systems the sync to burst posi- tion can change line to line by as much as 140 ns (the period of a 2FSC clock cycle) due to the fact that the burst flag is generated from a clocked CSYNC while the sync is injected unclocked. This phenomenon may or may not create visual artifacts in some high- end video systems. APPLYING THE AD724 Inputs RIN, BIN, GIN are analog inputs that should be terminated to ground with 75 Ω in close proximity to the IC. When properly terminated the peak-to-peak voltage for a maximum input level should be 714 mV p-p. The horizontal blanking interval should be the most negative part of each signal. The inputs should be held at the input signal’s black level dur- ing the horizontal blanking interval. The internal dc clamps will clamp this level during color burst to a reference that is used internally as the black level. Any noise present on the RIN, GIN, BIN or AGND pins during this interval will be sampled onto the input capacitors. This can result in varying dc levels from line to line in all outputs or, if imbalanced, subcarrier feedthrough in the COMP and CRMA outputs. For increased noise rejection, larger input capacitors are desired. A capacitor of 0.1 µF is usually adequate. Similarly, the U and V clamps balance the modulators during an interval shortly after the falling CSYNC input. Noise present during this interval will be sampled in the modulators, resulting in residual subcarrier in the COMP and CRMA outputs. HSYNC and VSYNC are two logic level inputs that are combined internally to produce a composite sync signal. If a composite sync signal is to be used, it can be input to HSYNC while VSYNC is pulled to logic HI (> +2 V). The form of the input sync signal(s) will determine the form of the composite sync on the composite video (COMP) and lumi- nance (LUMA) outputs. If no equalization or serration pulses are included in the HSYNC input there won’t be any in the outputs. Although sync signals without equalization and serra- tion pulses do not technically meet the video standards’ specifi- cations, many monitors do not require these pulses in order to display good pictures. The decision whether to include these signals is a system tradeoff between cost and complexity and adhering strictly to the video standards. The HSYNC and VSYNC logic inputs have a small amount of built-in hysteresis to avoid interpreting noisy input edges as multiple sync edges. This is critical to proper device operation, as the sync pulses are timed for vertical blanking interval detection. The HSYNC and VSYNC inputs have been designed for VIL > 1.0 V and VIH < 2.0 V for the entire temperature and supply range of operation. The remaining logic inputs do not have hysteresis, and their switching points are centered around 1.4 V. This allows the AD724 to directly interface to TTL or 3 V CMOS compatible outputs, as well as 5 V CMOS outputs where VOL is less than 1.0 V. The SELECT input is a CMOS logic level that programs the AD724 to use a subcarrier at a 1FSC (LO) frequency or a 4FSC (HI) frequency for the appropriate standard being used. A 4FSC clock is used directly, while a 1FSC input is multiplied up to 4FSC by an internal phase locked loop. The FIN input can be a logic level clock at either FSC or 4FSC frequency or can be a parallel resonant crystal at 1FSC fre- quency. An on-chip oscillator will drive the crystal. Most crys- tals will require a shunt capacitance of between 10 pF and 30 pF for reliable start up and proper frequency of operation. The NTSC specification calls for a frequency accuracy of ±10 Hz from the nominal subcarrier frequency of 3.579545 MHz. While maintaining this accuracy in a broadcast studio might not be a severe hardship, it can be quite expensive in a low cost con- sumer application. The AD724 will operate with subcarrier frequencies that deviate quite far from those specified by the TV standards. However, the monitor will in general not be quite so forgiving. Most moni- tors can tolerate a subcarrier frequency that deviates several hun- dred Hz from the nominal standard without any degradation in picture quality. These conditions imply that the subcarrier fre- quency accuracy is a system specification and not a specification of the AD724 itself. The STND pin is used to select between NTSC and PAL opera- tion. Various blocks inside the AD724 use this input to program their operation. Most of the more common variants of NTSC and PAL are supported. There are, however, two known specific stan- dards not supported. These are NTSC 4.43 and M-PAL. Basically these two standards use most of the features of the standard that their names imply, but use the subcarrier that is equal to, or approximately equal to, the frequency of the other standard. Because of the automatic programming of the filters in the chrominance path and other timing considerations, it is not possible to support these standards. Layout Considerations The AD724 is an all CMOS mixed signal part. It has separate pins for the analog and digital +5 V and ground power supplies. |
Podobny numer części - AD724JR-REEL |
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Podobny opis - AD724JR-REEL |
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