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AD7226BCHIPS Arkusz danych(PDF) 10 Page - Analog Devices |
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AD7226BCHIPS Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 16 page REV. –10– AD7226 DAC A VREF VDD DGND AGND VSS VOUTA AD7226* *DIGITAL INPUTS OMITTED FOR CLARITY 5 VBIAS Figure 10. AGND Bias Circuit For a given VIN, increasing AGND above system GND will reduce the effective VDD–VREF which must be at least 4 V to ensure specified operation. Note that because the AGND pin is common to all four DACs, this method biases up the output voltages of all the DACs in the AD7226. Note that VDD and VSS of the AD7226 should be referenced to DGND. 3-PHASE SINE WAVE The circuit of Figure 11 shows an application of the AD7226 in the generation of 3-phase sine waves which can be used to con- trol small 3-phase motors. The proper codes for synthesizing a full sine wave are stored in EPROM, with the required phase- shift of 120 ∞ between the three D/A converter outputs being generated in software. Data is loaded into the three D/A converters from the sine EPROM via the microprocessor or control logic. Three loops are generated in software with each D/A converter being loaded from a separate loop. The loops run through the look-up table producing successive triads of sinusoidal values with 120 ∞ separation which are loaded to the D/A converters producing three sine wave voltages 120 ∞ apart. A complete sine wave cycle is generated by stepping through the full look-up table. If a 256-element sine wave table is used then the resolution of the circuit will be 1.4 ∞ (360∞/256). Figure 13 shows typical resulting waveforms. The sine waves can be smoothed by filter- ing the D/A converter outputs. The fourth D/A converter of the AD7226, DAC D, may be used in a feedback configuration to provide a programmable reference voltage for itself and the other three converters. This configuration is shown in Figure 11. The relationship of VREF to VIN is dependent upon digital code and upon the ratio of RF to R and is given by the formula. V G GD V REF D IN = + () +¥ () ¥ 1 1 (6) where G = RF/R and DD is a fractional representation of the digital word in latch D. Alternatively, for a given VIN and resistance ratio, the required value of DD for a given value of VREF can be determined from the expression DR R V V R R DF IN REF F =+ ()¥ 1 /– (7) Figure 12 shows typical plots of VREF versus digital code for three different values of RF. With VIN = 2.5 V and RF = 3 R the peak-to-peak sine wave voltage from the converter outputs will vary between 2.5 V and 10 V over the digital input code range of 0 to 255. DIGITAL CODE (Decimal Equivalent) 4.0 V IN 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 3.5 V IN 3.0 V IN 2.5 V IN 2.0 V IN 1.5 V IN VIN RF = 3R RF = 2R RF = R VDD = +15 V VSS = –5 V Figure 12. Variation of VREF with Feedback Configuration VREF VOUTA WR A1 A0 VOUTB VOUTC VOUTD AD7226 DATA BUS ADDRESS BUS MICROPROCESSOR OR CONTROL LOGIC SINE EPROM ADDRESS DECODE VIN RF R Figure 11. 3-Phase Sine Wave Generation Circuit VOUTA VOUTB VOUTC Figure 13. 3-Phase Sine Wave Output D |
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