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AD9139 Arkusz danych(PDF) 2 Page - Analog Devices

Numer części AD9139
Szczegółowy opis  16-Bit, 1600 MSPS, TxDAC Digital-to- Analog Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9139 Arkusz danych(HTML) 2 Page - Analog Devices

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AD9139
Data Sheet
Rev. 0 | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 5
Latency Variation Specifications ................................................ 6
AC Specifications.......................................................................... 6
Operating Speed Specifications.................................................. 6
Absolute Maximum Ratings ....................................................... 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 15
Serial Port Operation ..................................................................... 16
Data Format ................................................................................ 16
Serial Port Pin Descriptions...................................................... 16
Serial Port Options..................................................................... 16
Data Interface.................................................................................. 18
LVDS Input Data Ports.............................................................. 18
Word Interface Mode................................................................. 18
Byte Interface Mode ................................................................... 18
Data Interface Configuration Options .................................... 18
DLL Interface Mode................................................................... 18
Parity ............................................................................................ 21
SED Operation............................................................................ 21
SED Example............................................................................... 22
Delay Line Interface Mode........................................................ 22
FIFO Operation .............................................................................. 24
Resetting the FIFO ..................................................................... 25
Serial Port Initiated FIFO Reset ............................................... 25
Frame Initiated FIFO Reset....................................................... 25
Digital Datapath.............................................................................. 27
Interpolation Filters ................................................................... 27
Inverse Sinc Filter ....................................................................... 28
Digital Function Configuration................................................ 28
Multidevice Synchronization and Fixed Latency....................... 29
Very Small Inherent Latency Variation................................... 29
Further Reducing the Latency Variation................................. 29
Synchronization Implementation ............................................ 29
Synchronization Procedures..................................................... 30
Interrupt Request Operation ........................................................ 32
Interrupt Working Mechanism ................................................ 32
Interrupt Service Routine.......................................................... 32
Temperature Sensor ....................................................................... 33
DAC Input Clock Configurations ................................................ 34
Driving the DACCLK and REFCLK Inputs ........................... 34
Direct Clocking .......................................................................... 34
Clock Multiplication .................................................................. 34
PLL Settings ................................................................................ 35
Configuring the VCO Tuning Band ........................................ 35
Automatic VCO Band Select .................................................... 35
Manual VCO Band Select ......................................................... 35
PLL Enable Sequence................................................................. 35
Analog Outputs............................................................................... 36
Transmit DAC Operation.......................................................... 36
Interfacing to Modulators ......................................................... 37
Reducing LO Leakage and Unwanted Sidebands .................. 38
Start-Up Routine ............................................................................ 39
Device Configuration Register Map and Description............... 40
SPI Configure Register .............................................................. 42
Power-Down Control Register ................................................. 42
Interrupt Enable 0 Register....................................................... 42
Interrupt Enable 1 Register....................................................... 42
Interrupt Flag 0 Register............................................................ 43
Interrupt Flag 1 Register............................................................ 43
Interrupt Select 0 Register......................................................... 43
Interrupt Select 1 Register......................................................... 44
Frame Mode Register................................................................. 44
Data Control 0 Register............................................................. 44
Data Control 1 Register............................................................. 44
Data Control 2 Register............................................................. 45
Data Control 3 Register............................................................. 45
Data Status 0 Register ................................................................ 45
DAC Clock Receiver Control Register .................................... 46
Reference Clock Receiver Control Register............................ 46


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