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AD7233ANZ Arkusz danych(PDF) 4 Page - Analog Devices |
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AD7233ANZ Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 8 page AD7233 REV. B –4– PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 1VDD Positive Supply (12 V to 15 V). 2 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge. 3 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input. 4 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a new data word. 5 LDAC Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of this signal, or alternatively if this line in permanently low, an automatic update mode is selected whereby the DAC is updated on the 16th falling SCLK pulse. 6 GND Ground Pin = 0 V. 7VOUT Analog Output Voltage. This is the buffered DAC output voltage (–5 V to +5 V). 8VSS Negative Supply (–12 V to –15 V). DIGITAL INTERFACE The AD7233 contains an input serial to parallel shift register and a DAC latch. A simplified diagram of the input loading cir- cuitry is shown in Figure 2. Serial data on the SDIN input is loaded to the input register under control of SYNC and SCLK. When a complete word is held in the shift register it may then be loaded into the DAC latch under control of LDAC. Only the data in the DAC latch determines the analog output on the AD7233. A low SYNC input provides the frame synchronization signal which tells the AD7233 that valid serial data on the SDIN input will be available for the next 16 falling edges of SCLK. An inter- nal counter/decoder circuit provides a low gating signal so that only 16 data bits are clocked into the input shift register. After 16 SCLK pulses the internal gating signal goes inactive (high) thus locking out any further clock pulses. Therefore, either a continuous clock or a burst clock source may be used to clock in the data. The SYNC input should be taken high after the complete 16-bit word is loaded in. Although 16 bits of data are clocked into the input register, only the latter 12 bits get transferred into the DAC latch. The first 4 bits in the 16-bit stream are don’t cares since their value does not affect the DAC latch data. Therefore the data format is 4 don’t cares followed by the 12-bit data word with the LSB as the last bit in the serial stream. CIRCUIT INFORMATION D/A Section The AD7233 contains a 12-bit voltage-mode D/A converter consisting of highly stable thin-film resistors and high-speed NMOS single-pole, double-throw switches. Op Amp Section The output of the voltage-mode D/A converter is buffered by a noninverting CMOS amplifier. The buffer amplifier is capable of developing ±5 V across a 2 kΩ load to GND. VOUT 2R 2R 2R DB11 2R DB10 R DB9 2R R R 2R DB1 DB0 2R R R 2R INTERNAL REFERENCE 5V GND Figure 1. Simplified D/A Converter TOP VIEW (Not to Scale) 8 7 6 5 1 2 3 4 VDD SCLK SDIN VSS VOUT GND LDAC SYNC AD7233 |
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