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AD7233ANZ Arkusz danych(PDF) 6 Page - Analog Devices

Numer części AD7233ANZ
Szczegółowy opis  LC2MOS 12-Bit Serial Mini-DIP DACPORT
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Strona internetowa  http://www.analog.com
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AD7233ANZ Arkusz danych(HTML) 6 Page - Analog Devices

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AD7233–Typical Performance Characteristics
REV. B
–6–
APPLYING THE AD7233
Bipolar ( 5 V) Configuration
The AD7233 provides an output voltage range from –5 V to
+5 V without any external components. This configuration is
shown in Figure 4. The data format is two’s complement. The
output code table is shown in Table I. If offset binary coding is
required, it can be done by inverting the MSB in software before
the data is loaded to the AD7233.
12-BIT
DAC
2R
2R
VDD
AD7233
+5V
VOUT
GND
VSS
–12V TO –15V
+12V TO +15V
Figure 4. Circuit Configuration
Power Supply Decoupling
To achieve optimum performance when using the AD7233, the
VDD and VSS lines should each be decoupled to GND using
0.1
µF capacitors. In very noisy environments it is recom-
mended that 10
µF capacitors be connected in parallel with
the 0.1
µF capacitors.
Table I. AD7233 Bipolar Code Table
Input Data Word
MSB
LSB
Analog Output, VOUT
XXXX 0111 1111 1111
+5 V • (2047/2048)
XXXX 0000 0000 0001
+5 V • (1/2048)
XXXX 0000 0000 0000
0 V
XXXX 1111 1111 1111
–5 V • (1/2048)
XXXX 1000 0000 0001
–5 V • (2047/2048)
XXXX 1000 0000 0000
–5 V • (2048/2048) = –5 V
X = Don’t Care
Note: 1 LSB = 5 V/2048
≈ 2.4 mV
100
0
100k
20
10
1k
10
40
30
50
60
70
80
90
100
10k
FREQUENCY – Hz
OUTPUT WITH ALL
0s ON DAC
DD
POWER SUPPLY DECOUPLING CAPACITORS
ARE 10 F AND 0.1 F.
*
OUTPUT WITH ALL
1s ON DAC
DECOUPLING
NO DECOUPLING
DECOUPLING
NO DECOUPLING
V = 15V WITH
100mV p-p SIGNAL
TPC 2. Power Supply Rejection
Ratio vs. Frequency
VDD /VSS – Volts
0.50
10.5
0.40
0.30
0.20
0.10
0.00
11
12
13
14
15
16
TA = 25 C
TPC 1. Linearity vs. Power Supply
Voltage
500
0
100k
20
5k
50
50
100
200
100 200 500 1k 2k
10k 20k
50k
FREQUENCY – Hz
OUTPUT WITH ALL
0s ON DAC
VDD = +15V
VSS = –15V
TA = 25 C
TPC 3. Noise Spectral Density
vs. Frequency


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