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TLP700 Arkusz danych(PDF) 1 Page - Toshiba Semiconductor

Numer części TLP700
Szczegółowy opis  Industrial inverters Inverter for air conditioners IGBT/Power MOSFET gate drive
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Producent  TOSHIBA [Toshiba Semiconductor]
Strona internetowa  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TLP700 Arkusz danych(HTML) 1 Page - Toshiba Semiconductor

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TLP700
2010-02-23
1
Unit in mm
Weight: 0.26 g (t yp.)
4.58±0.25
9.7±0.3
0.4±0.1
1.27±0.2
1.25±0.25
7.62±0.25
1 2 3
6 5 4
11-5J1
TOSHIBA
11-5J1
TOSHIBA Photocoupler GaAℓAs IRED + Photo IC
TLP700
Industrial inverters
Inverter for air conditioners
IGBT/Power MOSFET gate drive
TLP700 consists of a GaAℓAs light-emitting diode and an integrated
photodetector.
This unit is 6-lead SDIP package. The TLP700 is 50% smaller than the 8-pin
DIP and meets the reinforced insulation class requirements of international safety
standards. Therefore the mounting area can be reduced in equipment requiring
safety standard certification.
The TLP700 is suitable for gate driving circuits for IGBTs or power MOSFETs.
In particular, the TLP700 is capable of “direct” gate driving of low-power IGBTs.
• Peak output current:
±2.0 A (max)
• Guaranteed performance over temperature: −40 to 100°C
• Supply current:
2 mA (max)
• Power supply voltage:
15 to 30 V
• Threshold input current:
IFLH = 5 mA (max)
• Switching time (tpLH / tpHL):
500 ns (max)
• Common mode transient immunity:
±15 kV/μs (min)
• Isolation voltage:
5000 Vrms (min)
• Construction mechanical rating
7.62-mm pitch
standard type
10.16-mm pitch
TLPXXXF type
Creepage Distance
Clearance
Insulation Thickness
7.0 mm (min)
7.0 mm (min)
0.4 mm (min)
8.0 mm (min)
8.0 mm (min)
0.4 mm (min)
UL recognized:
UL1577, File No. E67349
Option (D4) type
TÜV approved:
EN60747-5-2
Maximum operating insulation voltage: 890 Vpk
Highest permissible over voltage:
8000 Vpk
( Note ) When a EN60747-5-2 approved type is needed,
please designate the “Option(D4)”
Truth Table
Input
LED
M1
M2
Output
H
ON
ON
OFF
H
L
OFF
OFF
ON
L
1: ANODE
2: N.C
3: CATHODE
4: GND
5: VO ( OUTPUT )
6: VCC
1
3
4
5
6
2
SHIELD
Pin Configuration (Top View)
A 0.1-
μF bypass capacitor must be connected
between pins 6 and 4. (See Note 6.)
Schematic
VCC
GND
ICC
(M1)
(M2)
IO
IF
1+
4
5
6
VO
VF
3-
SHIELD


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