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AD9215BRU-65EB Arkusz danych(PDF) 11 Page - Analog Devices

Numer części AD9215BRU-65EB
Szczegółowy opis  High Speed ADC USB FIFO Evaluation Kit
Download  28 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9215BRU-65EB Arkusz danych(HTML) 11 Page - Analog Devices

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HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
Rev. 0 | Page 11 of 28
JUMPERS
Use the legends in Table 3 and Table 4 to configure the jumpers. On the FIFO evaluation board, Channel A is associated with the bottom
IDT FIFO chip, and Channel B is associated with the top IDT FIFO chip (closest to the Analog Devices logo).
Table 3. Jumper Legend
Position
Description
In
Jumper in place (2-pin header).
Out
Jumper removed (2-pin header).
Position 1 or Position 3
Denotes the position of a 3-pin header. Position 1 is marked on the board.
Table 4. Solder Jumper Legend
Position
Description
In
Solder pads should be connected with 0 Ω resistor.
Out
Solder pads should not be connected with 0 Ω resistor.
DEFAULT SETTINGS
Table 5 lists the default settings for each model of the FIFO evaluation kit. The single channel (SC) model is configured to work with a
single channel ADC using the bottom FIFO, U201. The dual channel (DC) model is configured to work with demultiplexed ADCs (such
as the AD9430). Dual channel ADC settings are shown in a separate column, as are settings for the opposite (top) FIFO, U101 for a single
channel ADC. To align the timing properly, some evaluation boards require modifications to these settings. Refer to the Clocking
Description section in the Theory of Operation section for more information.
Another useful way to configure the jumper settings easily for various configurations is to consult ADC Analyzer under Help > About
HSC_ADC_EVALB
, and click Set Up Default Jumper Wizard. Then click the configuration setting that applies to the application of
interest. A picture of the FIFO board is displayed for that application with a visual of the correct jumper settings already in place.
Table 5. Jumper Configurations
Jumper #
Single Channel
Settings, Default
(Bottom)
Demultiplexed
Settings
Dual-Channel
Settings
Single-Channel
Settings (Top)1
Description
J303
In
Out
Out
In
Position 2 to Position 4, ties write clocks together
J304
In
In
In
In
Position 1 to Position 2, POS3: invert clock out of
DS90 (U301)
J305
In
In
In
In
Position 2 to Position 3, POS3: invert clock out of
DS90 (U301)
J306
Out
Out
Out
Out
No invert to encode clock from XOR (U302),
0 Ω resistor
J307
Out
Out
Out
Out
No invert to encode clock from XOR (U302),
0 Ω resistor
J310 to
J313
In
In
In
In
All solder jumpers are shorted with 0 Ω resistors
(bypass level shifting to input of DS90)
J314
In
In
In
In
Position 1 to Position 2, one XOR gate timing
delay for top FIFO (U101)
J315
In
In
In
In
Position 1 to Position 2, one XOR gate timing
delay for bottom FIFO (U201)
J316
In
In
In
In
Power connected using switching power supply
J401
In
In
In
In
Controls if top FIFO (U101) gets write enable
before or after bottom FIFO, 0 Ω resistor
J402
Out
Out
Out
Out
Controls if top FIFO (U101) gets write enable
before or after bottom FIFO, 0 Ω resistor
J403
Out
Out
Out
Out
Controls if bottom FIFO (U201) gets a write
enable before or after the top FIFO, 0 Ω resistor
J404
In
In
In
In
Controls if bottom FIFO (U201) gets a write
enable before or after the top FIFO, 0 Ω resistor
J405
Out
In
Out
Out
When in, WRT_CLK1 is used to create write enable
signal for FIFOs, 0 Ω resistor (significant only for
interleave mode)


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