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AD9066JR-REEL Arkusz danych(PDF) 5 Page - Analog Devices |
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AD9066JR-REEL Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 7 page AD9066 REV. A –5– Timing The duty cycle of the encode clock for the AD9066 is critical in obtaining rated performance of the ADC. Rated maximum and minimum pulse widths should be maintained, especially for sample rates greater than 40 MSPS. The AD9066 provides latched data outputs with three pipeline delays. The length and load on the output data lines should be minimized to reduce power supply transients inside the AD9066 which might diminish dynamic performance. N N + 1 N + 2 tA tV tPD DATA CHANGING ANALOG INPUT ENCODE D0–D5 VALID DATA FOR N–3 VALID DATA FOR N–2 VALID DATA FOR N–1 Figure 5. Timing Diagram The data is invalid during the period between tV and tPD. This period refers to the time required for the AD9066 to fully switch between valid CMOS logic levels. When latching the output data, be careful to observe latch setup and hold time restrictions as well as this data invalid period when designing the system timing. Layout and Signal Care To insure optimum performance, a single low impedance ground plane is recommended. Analog and digital grounds should be connected together at the AD9066. Analog and digi- tal power supplies should be bypassed, at the device, to ground through 0.1 µF ceramic capacitors. The use of sockets may limit the dynamic performance of the part and is not recommended except for prototype or evaluation purposes. Driving the AD9066 with a Bipolar Input The analog input range of the AD9066 is between 3.7 V and 4.2 V. Because the input is offset, the normal method of driving the analog input is to use a blocking capacitor between the ana- log source and the AD9066 analog input pins. In applications where DC coupling must be employed, the simple circuit shown in Figure 6 will take a bipolar input and offset it to the operating range of the AD9066. To offset the input, the midpoint voltage of the AD9066 is buff- ered off chip and then inverted with an AD712, a low input bias current dual op amp. This inverted midpoint is then fed to a summation amplifier that combines the bipolar input with the inverted offset voltage. The summation amplifier is an AD812, a wideband current feedback amplifier that provides good band- width and low distortion. + + + AD9066 6 BITS 6 BITS ENCODE INA REF A OR REF B INB 1/2 AD712 2k 1/2 AD712 1/2 AD812 1/2 AD812 866 866 2k 866 866 866 866 –15V +15V Figure 6. Bipolar Input Using AD812 Drive for AD9066 Layout should follow high frequency/high speed design guide- lines. In addition the capacitance around the inverting input to the AD812 should be minimized through a tight layout and the use of low capacitance chip resistors for gain setting. Quadrature Receiver Using the AD9066 Although any type of input signal may be applied, the AD9066 has been optimized for low cost in-phase and quadrature (I and Q) demodulators. Primary applications include digital direct broadcast satellite applications where broadband quadrature phase shift keying (QPSK) modulation is used. In these receivers the recovered signal is separated into I and Q vector components and digitized. AD9066 ADC ADC LPF LPF VCO VCO 90 IF IN Figure 7. Simplified Block Diagram For data symbol rates less than 10 Mbaud, the AD607 IF/RF receiver subsystem provides an ideal solution for the second conversion stage of a complete receiver system. Figure 8 shows the AD9066 and AD607 used together. The AD607 accepts inputs as high as 500 MHz which may be the output of the first IF stage or RF signals directly. The IF/RF signal is mixed with the local oscillator to provide an IF fre- quency of 400 kHz to 22 MHz. This signal is filtered externally and then amplified with an on-chip AGC before being synchro- nously demodulated with an on-chip PLL carrier recovery circuit. The outputs are digitized with the AD9066. The digital outputs may be processed with a DSP chip such as the ADSP- 2171, ADSP-21062, general purpose DSP or ASIC. |
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