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AD9203 Arkusz danych(PDF) 11 Page - Analog Devices |
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AD9203 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 28 page AD9203 Rev. B | Page 11 of 28 OPERATIONS THEORY OF OPERATION The AD9203 implements a pipelined multistage architecture to achieve high sample rates while consuming low power. It distributes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, the AD9203 requires a small fraction of the 1023 comparators used in a traditional 10-bit flash-type A/D. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Each stage of the pipeline, excluding the last, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D. The input of the AD9203 incorporates a novel structure that merges the input sample-and-hold amplifier (SHA) and the first pipeline residue amplifier into a single, compact switched capacitor circuit. This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. By matching the sampling network of the input SHA with the first stage flash A/D, the AD9203 can sample inputs well beyond the Nyquist frequency with no degradation in performance. Sampling occurs on the falling edge of the clock. OPERATIONAL MODES The AD9203 may be connected in several input configurations, as shown in Table 4. The AD9203 may be driven differentially from a source that keeps the signal peaks within the power supply rails. Alternatively, the input may be driven into AINP or AINN from a single-ended source. The input span will be 2 the programmed reference voltage. One input will accept the signal, while the opposite input will be set to midscale by connecting it to the internal or an external reference. For example, a 2 V p-p signal may be applied to AINP while a 1 V reference is applied to AINN. The AD9203 will then accept a signal varying between 2 V and 0 V. See Figure 19, Figure 20, and Figure 21 for more details. The single-ended (ac-coupled) input of the AD9203 may also be clamped to ground by the internal clamp switch. This is accomplished by connecting the CLAMP pin to AINN or AINP. Digital output formats may be configured in binary and twos complement. This is determined by the potential on the DFS pin. If the pin is set to Logic 0, the data will be in straight binary format. If the pin is asserted to Logic 1, the data will be in twos complement format. Power consumption may be reduced by placing a resistor between PWRCON and AVSS. This may be done to conserve power when not encoding high-speed analog input frequencies or sampling at the maximum conversion rate. See the Power Control section for more information. Table 4. Modes Name Figure Number Advantages 1 V Differential Figure 28 with VREF Connected to REFSENSE Differential Modes Yield the Best Dynamic Performance 2 V Differential Figure 28 with REFSENSE Connected to AGND Differential Modes Yield the Best Dynamic Performance 1 V Single-Ended Figure 20 Video and Applications Requiring Clamping Require Single-Ended Inputs 2 V Single-Ended Figure 19 Video and Applications Requiring Clamping Require Single-Ended Inputs |
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