Signal Description

Signal

DIP

PLCC

I/O/Z

Description

Pinout

Pinout

Note: Please see the following definitions: DIP = Dual In-line Package

PLCC = Plastic Leaded Chip Carrier

D15-D8

18-11

13-17, 19-21

I/O/Z

Unused. Leave open.

D7-D0

19-26

22-28, 30

I/O/Z

8-bit coprocessor latch.

TBLF

40

44

O

Transmit buffer latch full flag.

RBLE

1

2

O

Receive buffer latch empty flag

HI/LO

2

3

I

Latch byte select pin. Tie low.

BIO

9

10

I

Unused. Leave open.

RD

32

36

I/O

Used by the external processor to read from the coprocessor

latch by driving the RD line active (low), thus enabling the output

latch to drive the latched data. When the data has been read, the

external device must bring the RD line high.

EXINT

5

6

I

Unused. Leave open.

MC

3

4

I

Microcomputer mode select pin. Tie low.

MC/PM

27

31

I

Coprocessor mode select pin. Tie low.

RS

4

5

I

Reset input for initializing the device. When an active low is placed

on RS pin for a minimum of five clock cycles, RD and WR are

forced high, and the data bus (D7 through D0) goes to a high

impedance state. The serial port clock and transmit outputs also go

to the high impedance state.

WR

31

35

I/O

Used by the external processor to write data to the coprocessor

port. To write data the external processor drives the WR line low,

places data on the data bus, and then drives the WR line high to

clock the data into the on-chip latch.

XF

28

32

O

Watchdog signal. Toggles at least once every 15 milliseconds when

the processor is functioning properly. If the pin is not toggled at

least once every 15 ms, the processor is lost and should be reset.

CLKOUT

6

7

O

System clock output (one-fourth crystal/CLKIN frequency,

nominally 5.12 MHz).

V

CC

30

34

I

5V supply pin.

V

SS

10

1, 12, 18, 29

I

Ground pin.

X1

7

8

O

Crystal output pin for internal oscillator. If an internal oscillator is

not used, this pin should be left unconnected.

X2/CLKIN

8

9

I

Input pin to the internal oscillator (X2) from the crystal.

Alternatively, an input pin for the external oscillator (CLKIN).

DR1 & DR0

33 & 29

37, 33

I

Serial-port receive-channel inputs. 2.048 MHz serial data is received

in the receive registers via these pins. DR0 = channel 1; DR1 =

channel 2

DX1 & DX0

36 & 35

40, 39

O

Serial-port transmit-channel outputs. 2.048 MHz serial data is

transmitted from the transmit registers on these pins.These outputs

are in the high-impedance state when not transmitting.

M-986-2R2

www.clare.com

5

Rev. 3

External Clock Option: An external frequency source

can be used by injecting the frequency directly in

X2/CLKIN, with X1 left unconnected. The external fre-

quency injected must conform to the specifications list-

ed in the External Frequency specification Table on

page 7.

Flammability/Reliability Specifications

Reliability:

185 FITS failures/billion hours

Flammability:

Passes UL 94 V-0 tests