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PD10256H Arkusz danych(PDF) 1 Page - Data Delay Devices, Inc.

Numer części PD10256H
Szczegółowy opis  8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H)
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Producent  DATADELAY [Data Delay Devices, Inc.]
Strona internetowa  http://www.datadelay.com
Logo DATADELAY - Data Delay Devices, Inc.

PD10256H Arkusz danych(HTML) 1 Page - Data Delay Devices, Inc.

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PDU10256H
8-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU10256H)
FEATURES
PACKAGES
Digitally programmable in 128 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits 48-pin DIP socket
PIN DESCRIPTIONS
IN
Signal Input
OUT Signal Output
A0-A7 Address Bits
ENB Output Enable
VEE
-5 Volts
GND Ground
FUNCTIONAL DESCRIPTION
The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TDA, from the
input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following
formula:
TDA = TD0 + TINC * A
where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of
the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns
through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this signal is
brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain asserted
during normal operation.
SERIES SPECIFICATIONS
data
delay
devices, inc.
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
ENB
IN
N/C
N/C
A2
A1
VEE
A0
N/C
A5
A4
VEE
A3
N/C
N/C
N/C
N/C
N/C
N/C
A7
VEE
A6
GND
IN
A6
VEE
GND
ENB
A0
VEE
48
47
42
41
1
2
7
8
GND
OUT
A1
A2
GND
A3
VEE
40
34
33
9
15
16
GND
A4
A5
32
25
17
19
23
24
GND
A7
P
P
PDU10256H-xxC5
SMD
PDU10256H-xxMC5 Mil SMD
DU10256H-xx DIP
DU10256H-xxM Mil DIP
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
Total
Delay (ns)
PDU10256H-.5
0.5
± 0.3
127.5
± 6.4
PDU10256H-1
1.0
± 0.5
255
± 12.8
PDU10256H-2
2.0
± 0.5
510
± 25.5
PDU10256H-3
3.0
± 1.0
765
± 38.2
PDU10256H-4
4.0
± 1.0
1020
± 51.0
PDU10256H-5
5.0
± 1.5
1275
± 63.8
PDU10256H-6
6.0
± 1.5
1530
± 76.5
PDU10256H-8
8.0
± 2.0
2040
± 102
PDU10256H-10
10.0
± 2.0
2550
± 128
NOTE: Any dash number between .5 and 10
not shown is also available.
Total programmed delay tolerance: 5% or 2ns,
whichever is greater
Inherent delay (TD0): 12ns typical
Setup time and propagation delay:
Address to input setup (TAIS):
3.6ns
Disable to output delay (TDISO): 1.7ns typical
Operating temperature: 0
° to 70° C
Temperature coefficient: 100PPM/
°C (excludes TD0)
Supply voltage VEE: -5VDC ± 5%
Power Dissipation: 925mw typical (no load)
Minimum pulse width: 16% of total delay
2009 Data Delay Devices
Doc #97047
DATA DELAY DEVICES, INC.
1
2/9/2009
3 Mt. Prospect Ave. Clifton, NJ 07013


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