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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AD2S1210-EP Arkusz danych(PDF) 5 Page - Analog Devices |
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AD2S1210-EP Arkusz danych(HTML) 5 Page - Analog Devices |
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5 / 16 page  AD2S1210-EP Rev. 0 | Page 5 of 16 TIMING SPECIFICATIONS AVDD = DVDD = 5.0 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.1 Table 2. Parameter Description Limit at T MIN, TMAX Unit f CLKIN Frequency of clock input 6.144 MHz min 10.24 MHz max t CK Clock period (t CK = 1/fCLKIN) 98 ns min 163 ns max t 1 A0 and A1 setup time before RD/CS low 2 ns min t 2 Delay CS falling edge to WR/FSYNC rising edge 22 ns min t 3 Address/data setup time during a write cycle 3 ns min t 4 Address/data hold time during a write cycle 2 ns min t 5 Delay WR/FSYNC rising edge to CS rising edge 2 ns min t 6 Delay CS rising edge to CS falling edge 10 ns min t 7 Delay between writing address and writing data 2 × t CK + 20 ns min t 8 A0 and A1 hold time after WR/FSYNC rising edge 2 ns min t 9 Delay between successive write cycles 6 × t CK + 20 ns min t 10 Delay between rising edge of WR/FSYNC and falling edge of RD 2 ns min t 11 Delay CS falling edge to RD falling edge 2 ns min t 12 Enable delay RD low to data valid in configuration mode V DRIVE = 4.5 V to 5.25 V 37 ns min V DRIVE = 2.7 V to 3.6 V 25 ns min V DRIVE = 2.3 V to 2.7 V 30 ns min t 13 RD rising edge to CS rising edge 2 ns min t 14A Disable delay RD high to data high-Z 16 ns min t 14B Disable delay CS high to data high-Z 16 ns min t 15 Delay between rising edge of RD and falling edge of WR/FSYNC 2 ns min t 16 SAMPLE pulse width 2 × t CK + 20 ns min t 17 Delay from SAMPLE before RD/CS low 6 × t CK + 20 ns min t 18 Hold time RD before RD low 2 ns min t 19 Enable delay RD/CS low to data valid V DRIVE = 4.5 V to 5.25 V 17 ns min V DRIVE = 2.7 V to 3.6 V 21 ns min V DRIVE = 2.3 V to 2.7 V 33 ns min t 20 RD pulse width 6 ns min t 21 A0 and A1 set time to data valid when RD/CS low V DRIVE = 4.5 V to 5.25 V 36 ns min V DRIVE = 2.7 V to 3.6 V 37 ns min V DRIVE = 2.3 V to 2.7 V 29 ns min t 22 Delay WR/FSYNC falling edge to SCLK rising edge 3 ns min t 23 Delay WR/FSYNC falling edge to SDO release from high-Z V DRIVE = 4.5 V to 5.25 V 16 ns min V DRIVE = 2.7 V to 3.6 V 26 ns min V DRIVE = 2.3 V to 2.7 V 29 ns min t 24 Delay SCLK rising edge to DBx valid V DRIVE = 4.5 V to 5.25 V 24 ns min V DRIVE = 2.7 V to 3.6 V 18 ns min V DRIVE = 2.3 V to 2.7 V 32 ns min t 25 SCLK high time 0.4 × t SCLK ns min t 26 SCLK low time 0.4 × t SCLK ns min t 27 SDI setup time prior to SCLK falling edge 3 ns min t 28 SDI hold time after SCLK falling edge 2 ns min |
Podobny numer części - AD2S1210-EP |
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Podobny opis - AD2S1210-EP |
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