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MC-458CA721ESA-A80 Arkusz danych(PDF) 1 Page - NEC

Numer części MC-458CA721ESA-A80
Szczegółowy opis  8M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM
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Producent  NEC [NEC]
Strona internetowa  http://www.nec.com/
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MC-458CA721ESA-A80 Arkusz danych(HTML) 1 Page - NEC

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©
1999
MOS INTEGRATED CIRCUIT
MC-458CA721ESA, 458CA721PSA
8M-WORD BY 72-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Document No. M14494EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
DATA SHEET
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark
• shows major revised points.
Description
The MC-458CA721ESA and MC-458CA721PSA are 8,388,608 words by 72 bits synchronous dynamic RAM module
(Small Outline DIMM) on which 5 pieces of 128M SDRAM:
µPD45128163 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 8,388,608 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency (MAX.)
Access time from CLK (MAX.)
MC-458CA721ESA-A80
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
6 ns
MC-458CA721ESA-A10
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
MC-458CA721PSA-A80
CL = 3
125 MHz
6 ns
CL = 2
100 MHz
6 ns
MC-458CA721PSA-A10
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0, BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3V ± 0.3V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
5
5


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