Zakładka z wyszukiwarką danych komponentów |
|
AD1843 Arkusz danych(PDF) 7 Page - Analog Devices |
|
AD1843 Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 64 page AD1843 REV. 0 –7– PIN CONFIGURATIONS 80-Lead PQFP 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 80 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 AD1843 TOP VIEW (Not to Scale) GNDD XCTL1 XCTL0 SYNC3 SYNC2 SYNC1 GNDD VDD RESET PWRDWN VDD PDMNFT GNDA HPOUTL HPOUTC HPOUTR VCC SUML SUMR VCC VDD VCC SDO SDFS GNDD TSI TSO GNDD VDD CS BM AUX3R AUX3L AUX2R AUX2L AUX1R AUX1L MICR MICL MIN PIN DESCRIPTION Serial Interface Pin Name PQFP TQFP I/O Description SCLK 79 99 I/O Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output to the serial bus when the Bus Master (BM) pin is driven HI and accepts the clock as an input when the BM pin is driven LO. When the AD1843 is configured in master mode, the SCLK frequency may be set to either 12.288 MHz or 16.384 MHz with the SCF bit in Control Register Address 26. SDFS 2 2 I/O Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame synchronization signal as an output to the serial bus when the Bus Master (BM) pin is driven HI and accepts the frame synchronization signal as an input when the BM pin is driven LO. SDI 80 100 I Serial Data Input. SDI is used by peripheral devices such as the host CPU or a DSP to supply control and playback data information to the AD1843. All control and playback transfers are 16 bits long, MSB first. SDO 1 1 O Serial Data Output. SDO is used to supply status/control register readback and capture data information to peripheral devices such as the host CPU or a DSP. All status/control register readback and capture data transfers are 16 bits long, MSB first. A three-state output driver is used on this pin. BM 10 12 I Bus Master. When BM is tied HI the AD1843 is the serial bus master. The AD1843 will then supply the serial clock (SCLK) and the frame sync (SDFS) signals for the serial bus. No more than one device (AD1843/CPU/DSP) should be configured as the serial bus master. When BM is tied LO, the AD1843 is con- figured as a bus slave, and will accept the SCLK and SDFS signals as inputs. The logic level on this pin must not be changed once RESET is deasserted (driven HI). |
Podobny numer części - AD1843_15 |
|
Podobny opis - AD1843_15 |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |