28F001BX-T28F001BX-B

Table 3 28F001BX Command Definitions

Command

Cycles

Req’d

Bus

Notes

First Bus Cycle

Second Bus Cycle

Operation Address Data Operation Address Data

Read ArrayReset

1

1

Write

X

FFH

Intelligent Identifier

3

2 3 4

Write

X

90H

Read

IA

IID

Read Status Register

2

3

Write

X

70H

Read

X

SRD

Clear Status Register

1

Write

X

50H

Erase SetupErase Confirm

2

2

Write

BA

20H

Write

BA

D0H

Erase SuspendErase Resume

2

Write

X

B0H

Write

X

D0H

Program SetupProgram

2

2 3

Write

PA

40H

Write

PA

PD

NOTES

1 Bus operations are defined in Table 2

4 Following the Intelligent Identifier command two read operations access manufacture and device codes

5 Commands other than those shown above are reserved by Intel for future device implementations and should not be

used

Read Status Register Command

The 28F001BX contains a Status Register which

may be read to determine when a program or erase

operation is complete and whether that operation

completed successfully The Status Register may be

read at any time by writing the Read Status Register

command (70H) to the Command Register After

writing this command all subsequent read opera-

tions output data from the Status Register until an-

other valid command is written to the Command

Register The contents of the Status Register are

latched on the falling edge of OE

or CE

which-

ever occurs last in the read cycle OE

or CE

date the Status Register latch The Read Status

Clear Status Register Command

The Erase Status and Program Status bits are set to

‘‘1’’ by the Write State Machine and can only be

reset by the Clear Status Register command These

bits indicate various failure conditions (see Table 4)

By allowing system software to control the resetting

of these bits several operations may be performed

(such as cumulatively programming several bytes or

erasing multiple blocks in sequence) The Status

Register may then be polled to determine if an error

occurred during that series This adds flexibility to

the way the device may be used

‘‘1’’ MUST be reset by system software before fur-

ther byte programs or block erases are attempted

To clear the Status Register the Clear Status Regis-

ter command (50H) is written to the Command Reg-

ister The Clear Status Register command is func-

9