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GS6042 Arkusz danych(PDF) 4 Page - Semtech Corporation |
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GS6042 Arkusz danych(HTML) 4 Page - Semtech Corporation |
4 / 21 page GS6042 Final Data Sheet Rev. 3 PDS-060055 May 2014 4 of 21 Proprietary and Confidential www.semtech.com 1. Pin Out 1.1 GS6042 Pin Assignment Figure 1-1: GS6042 Pin Out 1.2 GS6042 Pin Descriptions Ground Pad (bottom of package) GS6042 16-pin QFN (top view) 56 7 8 16 15 14 13 GAIN_SEL VEE_A SDI 1 2 3 4 SDI VEE_O DDO DDO OP_CTL 12 11 10 9 Table 1-1: GS6042 Pin Descriptions Pin Number Name Type Description 1 VEE_A Power Most negative power supply connection for the input buffer, core, and control circuits. Connect to ground. 2, 3 SDI, SDI Input Serial digital differential input. 4GAIN_SEL Input Flat Band Gain Control. Please refer to the DC Electrical Characteristics table for logic level threshold and compatibility. This pin is a +2.5V input that is tolerant to +3.3V levels. When HIGH, the device compensates for an additional 6dB of loss across the entire operating band. This pin has an internal pull-down resistor. 5, 6 AGC, AGC — External AGC capacitor connection. 7BYPASS Input EQ Bypass Control. Please refer to the DC Electrical Characteristics table for logic level threshold and compatibility. This pin is a +2.5V input that is tolerant to +3.3V levels. Forces the equalizer and DC-restore stages into Bypass mode when HIGH. No equalization occurs in this mode. This pin has an internal pull-down resistor. |
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