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AD5384 Arkusz danych(PDF) 9 Page - Analog Devices |
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AD5384 Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 33 page Data Sheet AD5384 Rev. C | Page 9 of 33 I2C Serial Interface DVDDx = 2.7 V to 5.5 V; AVDDx = 4.5 V to 5.5 V; AGNDx = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 6. Limit at TMIN, TMAX. Table 4. Parameter Min Typ Max Unit Description fSCL 400 kHz SCL clock frequency t1 2.5 μs SCL cycle time t2 0.6 μs SCL high time, tHIGH t3 1.3 μs SCL low time, tLOW t4 0.6 μs Start/repeated start condition hold time, tHD, STA t5 100 ns Data setup time, tSU,DAT t61 0.9 μs Data hold time, tHD,DAT 0 μs Data hold time, tHD,DAT t7 0.6 μs Setup time for repeated start, tSU,STA t8 0.6 μs Stop condition setup time, tSU, STO t9 1.3 μs Bus free time between a stop and a start condition, tBUF t10 300 ns Rise time of SCL and SDA when receiving, tR 0 ns Rise time of SCL and SDA when receiving (CMOS-compatible), tR t11 300 ns Fall time of SDA when transmitting, tF 0 ns Fall time of SDA when receiving (CMOS-compatible), tF 300 ns Fall time of SCL and SDA when receiving, tF 20 + 0.1Cb2 ns Fall time of SCL and SDA when transmitting, tF Cb 400 pF Capacitive load for each bus line 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of the SCL falling edge. 2 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDDx and 0.7 DVDDx. START CONDITION REPEATED START CONDITION STOP CONDITION t9 t3 t1 t11 t4 t10 t4 t5 t7 t6 t8 t2 SDA SCL Figure 6. I2C-Compatible Serial Interface Timing Diagram |
Podobny numer części - AD5384_15 |
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Podobny opis - AD5384_15 |
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