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AD5428 Arkusz danych(PDF) 4 Page - Analog Devices

Numer części AD5428
Szczegółowy opis  Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD5428 Arkusz danych(HTML) 4 Page - Analog Devices

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Data Sheet
AD5428/AD5440/AD5447
Rev. C | Page 3 of 32
SPECIFICATIONS1
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
AD5428
Resolution
8
Bits
Relative Accuracy
±0.25
LSB
Differential Nonlinearity
±1
LSB
Guaranteed monotonic
AD5440
Resolution
10
Bits
Relative Accuracy
±0.5
LSB
Differential Nonlinearity
±1
LSB
Guaranteed monotonic
AD5447
Resolution
12
Bits
Relative Accuracy
±1
LSB
Differential Nonlinearity
–1/+2
LSB
Guaranteed monotonic
Gain Error
±25
mV
Gain Error Temperature Coefficient
±5
ppm FSR/°C
Output Leakage Current
±5
nA
Data = 0x0000, TA = 25°C
±15
nA
Data = 0x0000
REFERENCE INPUT
Reference Input Range
±10
V
VREFA, VREFB Input Resistance
8
10
13
Input resistance TC = –50 ppm/°C
VREFA-to-VREFB Input
Resistance Mismatch
1.6
2.5
%
Typ = 25°C, max = 125°C
Input Capacitance
Code 0
3.5
pF
Code 4095
3.5
pF
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
1.7
V
VDD = 3.6 V to 5.5 V
1.7
V
VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL
0.8
V
VDD = 2.7 V to 5.5 V
0.7
V
VDD = 2.5 V to 2.7 V
Output High Voltage, VOH
VDD − 1
V
VDD = 4.5 V to 5.5 V, ISOURCE = 200 μA
VDD − 0.5
V
VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA
Output Low Voltage, VOL
0.4
V
VDD = 4.5 V to 5.5 V, ISINK = 200 μA
0.4
V
VDD = 2.5 V to 3.6 V, ISINK = 200 μA
Input Leakage Current, IIL
1
μA
Input Capacitance
4
10
pF
DYNAMIC PERFORMANCE
Reference-Multiplying BW
10
MHz
VREF = ±3.5 V p-p, DAC loaded all 1s
Output Voltage Settling Time
RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V
DAC latch alternately loaded with 0s and 1s
Measured to ±1 mV of FS
80
120
ns
Measured to ±4 mV of FS
35
70
ns
Measured to ±16 mV of FS
30
60
ns
Digital Delay
20
40
ns
Interface delay time
10% to 90% Settling Time
15
30
ns
Rise and fall times, VREF = 10 V, RLOAD = 100 Ω
Digital-to-Analog Glitch Impulse
3
nV-sec
1 LSB change around major carry, VREF = 0 V


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