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8XC196KC20 Arkusz danych(PDF) 7 Page - Intel Corporation

Numer części 8XC196KC20
Szczegółowy opis  COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
Download  25 Pages
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Producent  INTEL [Intel Corporation]
Strona internetowa  http://www.intel.com
Logo INTEL - Intel Corporation

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8XC196KC8XC196KC20
PIN DESCRIPTIONS
Symbol
Name and Function
VCC
Main supply voltage (5V)
VSS
Digital circuit ground (0V) There are multiple VSS pins all of which must be connected
VREF
Reference voltage for the AD converter (5V) VREF is also the supply voltage to the analog
portion of the AD converter and the logic used to read Port 0 Must be connected for AD
and Port 0 to function
ANGND
Reference ground for the AD converter Must be held at nominally the same potential as
VSS
VPP
Timing pin for the return from powerdown circuit This pin also supplies the programming
voltage on the EPROM device
XTAL1
Input of the oscillator inverter and of the internal clock generator
XTAL2
Output of the oscillator inverter
CLKOUT
Output of the internal clock generator The frequency of CLKOUT is
the oscillator
frequency
RESET
Reset input and open drain output
BUSWIDTH
Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus
cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH isa0an
8-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus
NMI
A positive transition causes a vector through 203EH
INST
Output high during an external memory read indicates the read is an instruction fetch INST
is valid throughout the bus cycle INST is activated only during external memory accesses
and output low for a data fetch
EA
Input for memory select (External Access) EA equal high causes memory accesses to
locations 2000H through 5FFFH to be directed to on-chip ROMEPROM EA equal to low
causes accesses to those locations to be directed to off-chip memory Also used to enter
programming mode
ALEADV
Address Latch Enable or Address Valid output as selected by CCR Both pin options
provide a signal to demultiplex the address from the addressdata bus When the pin is
ADV it goes inactive high at the end of the bus cycle ALEADV is activated only during
external memory accesses
RD
Read signal output to external memory RD is activated only during external memory reads
WR WRL
Write and Write Low output to external memory as selected by the CCR WR will go low for
every external write while WRL will go low only for external writes where an even byte is
being written WR WRL is activated only during external memory writes
BHE WRH
Bus High Enable or Write High output to external memory as selected by the CCR BHE will
go low for external writes to the high byte of the data bus WRH will go low for external
writes where an odd byte is being written BHE WRH is activated only during external
memory writes
READY
Ready input to lengthen external memory cycles for interfacing to slow or dynamic memory
or for bus sharing When the external memory is not being used READY has no effect
HSI
Inputs to High Speed Input Unit Four HSI pins are available HSI0 HSI1 HSI2 and HSI3
Two of them (HSI2 and HSI3) are shared with the HSO Unit
HSO
Outputs from High Speed Output Unit Six HSO pins are available HSO0 HSO1 HSO2
HSI3 HSO4 and HSO5 Two of them (HSO4 and HSO5) are shared with the HSI Unit
Port 0
8-bit high impedance input-only port These pins can be used as digital inputs andor as
analog inputs to the on-chip AD converter
Port 1
8-bit quasi-bidirectional IO port
Port 2
8-bit multi-functional port All of its pins are shared with other functions in the 80C196KC
Pins 26 and 27 are quasi-bidirectional
7


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