7-58

Specifications CA3194

Saturation Control Range (Terminal 3)

For control characteristic, see Figure 10.

0 - 5

Maximum Chroma Output Voltage (Terminal 2)

2.5

OSCILLATOR SECTION

Pull-In Range

Apply signal to lock.

±500

Hz

Static Phase Error

2

Deg./

100Hz

DEMODULATOR SECTION

R-Y Demodulator Conversion Gain

10

Ratio

B-Y Demodulator Conversion Gain

18

Ratio

G-Y/B-Y Matrix Ratio

0.2

Ratio

G-Y/R-Y Matrix Ratio

0.5

Ratio

Sub-Carrier and Harmonic Content at Outputs

No Chroma or Luma Input. Read residual carrier at outputs.

30

SANDCASTLE PULSE

Horizontal and Vertical Blanking Pedestal

2 - 5

V

Burst Gate Pulse

V

NOTES:

1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17.

2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals.

3. The reference voltage can be adjusted by changing the values of the voltage divider.

These conditions exist except as otherwise noted. See Figure 19 for test circuit (Continued)

PARAMETER

TEST CONDITIONS

TYPICAL

VALUE

UNITS

The chroma signal is externally separated from the video

signal by means of a bandpass or high-pass filter and

applied to pin 4. The burst is separated in the first chroma

stage and applied to the synchronous detector which pro-

vides information to sample-and-hold circuits for APC

(phase-locked loop), ACC (automatic chroma gain control)

and identification and killing. The 4.43MHz crystal oscillator

is phase-locked to the burst and provides 0 degrees and 90

degrees (via an external phase shifter) carriers to the

chroma demodulators. The burst and chroma amplitude at

the output of the first chroma amplifier is kept constant by

the automatic gain control.

The second chroma stage provides saturation control (pin 3)

which tracks the contrast control in the luminance channel.

This stage is also used for color killing.

A buffer stage drives the external PAL delay line. The sepa-

rated U and V signals are applied to pins 14 and 15, respec-

tively, and demodulated. A standard G-Y matrix is included

on the chip.

The luminance signal passes through the subcarrier trap

and through the luminance delay line and enters the chip at

pin 20. Contrast and brightness control is provided before

the luminance signal is combined with the color difference

signals in the Y matrix. Average and peak beam limiting cir-

cuits are controlled from pins 24 and 19.