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CA3338D Arkusz danych(PDF) 7 Page - Intersil Corporation

Numer części CA3338D
Szczegółowy opis  CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters
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Producent  INTERSIL [Intersil Corporation]
Strona internetowa  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA3338D Arkusz danych(HTML) 7 Page - Intersil Corporation

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10-17
Applications
The output of the CA3338 can be resistively divided to match a
doubly terminated 50
Ω or 75Ω line, although peak-to-peak
swings of less than 1V may result. The output magnitude will
also vary with the converter’s output impedance. Figure 5
shows such an application. Note that because of the HCT input
structure, the CA3338 could be operated up to +7.5V VDD and
VREF+ supplies and still accept 0V to 5V CMOS input voltages.
If larger voltage swings or better accuracy is desired, a high
speed output buffer, such as the HA-5033, HA-2542, or
CA3450, can be employed. Figure 6 shows a typical applica-
tion, with the output capable of driving
±2V into multiple 50Ω
terminated lines.
Operating and Handling Considerations
HANDLING
All inputs and outputs of CMOS devices have a network
for electrostatic protection during handling. Recom-
mended handling practices for CMOS devices are
described in AN6525. “Guide to Better Handling and
Operation of CMOS Integrated Circuits.”
OPERATING
Operating Voltage
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause the
absolute maximum ratings to be exceeded.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than VDD nor less than
VSS. Input currents must not exceed 20mA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal. All
unused input terminals must be connected to either VCC
or GND, whichever is appropriate.
NOTES:
1. Both VREF+ pin and 392Ω resistor should be
bypassed within 1/4 inch.
2. Keep nodal capacitance at CA3450 pin 3 as
low as possible.
3. VOUT Range = ±3V at CA3450.
CLOCK
8 DATA
+5V
15
16
14
8
1-7, 9
LE
D0 - D7
VDD
COMP
VSS
CA3338
VOUT
VREF+
VEE
12
13
11
10
R
VREF-
R
11
UP TO 5 OUTPUT LINES
FOR R = 75
Ω, 3 LINES
FOR R = 50
VOUT1
VOUTN
+3.00V AT 25mA
4.7
µF
TAN
4.7
µF TAN
4.7
µF
TAN
0.1
µF
CER.
0.1
µF
CER.
0.1
µF CER.
14
+6V
-6V
392
392
1%
10k
1k
3
4, 5, 12, 13
R
R
+
+
+
+
VOUT = ±1.5VPEAK
6
7, 8
9
+
-
CA3450
ADJUST
OFFSET
5pF
BITS
1%
FIGURE 6. CA3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES
TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND VREF
VREF+
VREF-
STEP SIZE
5.12V
0
0.0200V
5.00V
0
0.0195V
4.608V
0
0.0180V
2.56V
-2.56V
0.0200V
2.50V
-2.50V
0.0195V
Input Code
111111112 = FFHEX
111111102 = FE-
HEX
5.1000V
5.0800
4.9805V
4.9610
4.5900V
4.5720
2.5400V
2.5200
2.4805V
2.4610
100000012 = 81HEX
100000002 = 80HEX
011111112 = 7FHEX
2.5800
2.5600
2.5400
2.5195
2.5000
2.4805
2.3220
2.3040
2.2860
0.0200
0.0000
- 0.0200
0.0195
0.0000
-0.0195
000000012 = 01HEX
000000002 = 00HEX
0.0200
0.0000
0.0195
0.0000
0.0180
0.0000
-2.5400
-2.5600
-2.4805
-2.5000
CA3338, CA3338A


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