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CD4015 Arkusz danych(PDF) 1 Page - Intersil Corporation |
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CD4015 Arkusz danych(HTML) 1 Page - Intersil Corporation |
1 / 3 page 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation. CD4015BT CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. CD4015BT consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages are D type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one CD4015BT, or to more than 8 stages using additional CD4015BT’s is possible. Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the CD4015BT are contained in SMD 5962-96624. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil’s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp Features • QML Class T, Per MIL-PRF-38535 • Radiation Performance - Gamma Dose ( γ) 1 x 105 RAD(Si) - SEP Effective LET > 75 MEV/gm/cm2 • Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V • Fully Static Operation • 8 Master-Slave Flip-Flops Plus Input and Output Buffering • 100% Tested For Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics Pinouts CD4015BT (SBDIP), CDIP2-T16 TOP VIEW CD4015BT (FLATPACK), CDFP4-F16 TOP VIEW Ordering Information ORDERING NUMBER PART NUMBER TEMP. RANGE (oC) 5962R9662401TEC CD4015BDTR -55 to 125 5962R9662401TXC CD4015BKTR -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CLOCK B Q4B Q3A Q2A Q1A RESET A VSS DATA A VDD RESET B Q1B Q2B Q3B Q4A CLOCK A DATA B CLOCK B Q4B Q3A Q2A Q1A RESET A DATA A VSS 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 VDD DATA B RESET B Q1B Q2B Q3B Q4A CLOCK A Data Sheet July 1999 File Number 4621.1 |
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