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CD4066BMS Arkusz danych(PDF) 1 Page - Intersil Corporation |
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CD4066BMS Arkusz danych(HTML) 1 Page - Intersil Corporation |
1 / 9 page 7-966 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4066BMS CMOS Quad Bilateral Switch Description CD4066BMS is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin for pin compatible with CD4016B, but exhibits a much lower on state resistance. In addition, the on-state resistance is relatively constant over the full input signal range. The CD4066BMS consists of four independent bilateral switches. A single control signal is required per switch. Both the p and the n device in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n channel device on each switch is either tied to the input when the switch is on or to VSS when the switch is off. This configuration eliminates the variation of the switch transistor threshold voltage with input signal, and thus keeps the on-state resistance low over the full operating signal range. The advantages over single channel switches include peak input signal voltage swings equal to the full supply voltage, and more constant on-state impedance over the input signal range. For sample and hold applications, however, the CD4016B is recommended. The CD4066BMS is supplied in these 14-lead outline pack- ages: Pinout CD4066BMS TOP VIEW Braze Seal DIP H4Q Frit Seal DIP H1B Ceramic Flatpack H3W IN/OUT A OUT/IN A OUT/IN B IN/OUT B CONT B CONT C VSS VDD CONT A CONT D IN/OUT D OUT/IN D OUT/IN C IN/OUT C 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Features • For Transmission or Multiplexing of Analog or Digital Signals • High Voltage Types (20V Rating) • 15V Digital or ±7.5V Peak-to-Peak Switching • 125 Ω Typical On-State Resistance for 15V Operation • Switch On-State Resistance Matched to Within 5 Ω Over 15V Signal Input Range • On-State Resistance Flat Over Full Peak-to-Peak Sig- nal Range • High On/Off Output Voltage Ratio - 80dB Typ. at FIS = 10kHz, RL = 1k Ω • High Degree of Linearity: <0.5% Distortion Typ. at FIS = 1kHz, VIS = 5Vp-p, VDD - VSS ≥ 10V, RL = 10kΩ • Extremely Low Off-State Switch Leakage Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10pA Typ. at VDD - VSS = 10V, TA = +25 oC • Extremely High Control Input Impedance (Control Cir- cuit Isolated from Signal Circuit): 1012 Ω Typ. • Low Crosstalk Between Switches: -50dB Typ. at FIS = 8MHz, RL = 1k Ω • Matched Control Input to Signal Output Capacitance: Reduces Output Signal Transients • Frequency Response, Switch on = 40MHz (Typ.) • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of “B” Series CMOS Devices” Applications • Analog Signal Switching/Multiplexing - Signal Gating - Modulator - Squelch Control - Demodulator - Chopper - Commutating Switch • Digital Signal Switching/Multiplexing • Transmission Gate Logic Implementation • Analog to Digital & Digital to Analog Conversion • Digital Control of Frequency, Impedance, Phase, and Analog Signal Gain December 1992 File Number 3319 |
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