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AD9060 Arkusz danych(PDF) 9 Page - Analog Devices

Numer części AD9060
Szczegółowy opis  10-Bit 75 MSPS A/D Converter
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Strona internetowa  http://www.analog.com
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AD9060 Arkusz danych(HTML) 9 Page - Analog Devices

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REV. B
AD9060
–9–
GND
DIGITAL BITS
AND OVERFLOW
Figure 6. Equivalent Digital Outputs
–VS
–VS
ENCODE
GND
ENCODE
Figure 7. ENCODE and
ENCODE Equivalent Circuits
Timing
In the AD9060, the rising edge of the ENCODE signal triggers
the A/D conversion by latching the comparators (see Figure 8).
These ENCODE and
ENCODE signals are ECL compatible and
should be driven differentially. Jitter on the ENCODE signal
will raise the noise floor of the converter. Differential signals,
with fast clean edges, will reduce the jitter in the signal and allow
optimum ac performance. In applications with a fixed, high
frequency encode rate, converter performance is also improved
(jitter reduced) by using a crystal oscillator as the system clock.
The AD9060 units are designed to operate with a 50% duty cycle
encode signal; adjustment of the duty cycle may improve the
dynamic performance of individual devices. Since the ENCODE
and
ENCODE signals are differential, the logic levels are not criti-
cal. Users should remember, however, that reduced logic levels
will reduce the slew rate of the edges and effectively increase the
jitter of the signal. ECL terminations for the ENCODE and
ENCODE signals should be as close as possible to the AD9060
package to avoid reflections.
In systems where only single-ended signals are available, the use of
a high speed comparator (such as the AD96685) is recommended
to convert to differential signals. An alternative is to connect
1.3 V (ECL midpoint) to
ENCODE and drive the ENCODE
connection single ended. In such applications, clean, fast edges
are necessary to minimize jitter in the signal.
N
N + 1
tA
tOD
DATA FOR N
DATA FOR N + 1
tA = APERTURE DELAY
tOD = OUTPUT DELAY
AIN
ENCODE
ENCODE
DATA OUTPUT
N
N + 1
Figure 8. Timing Diagram
Output data of the AD9060 (D0–D9 and OVERFLOW) are also
ECL compatible and should be terminated through 100
Ω to –2 V
(or an equivalent load).
Data Format
The format of the output data (D0–D9) is controlled by the
MSB INVERT and LSBs INVERT pins. These inputs are dc con-
trol inputs and should be connected to GND or +VS. Table I
gives information on how to choose from among binary, inverted
binary, twos complement, and inverted twos complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at +VSENSE. The accuracy of the
overflow transition voltage and output delay are not tested or
included in the data sheet limits. Performance of the overflow
indicator is dependent on the circuit layout and the slew rate of
the encode signal. The operation of this function does not affect
the other data bits (D0–D9). It is not recommended for applications
requiring a critical measure of analog input voltage.
Layout and Power Supplies
Proper layout of high speed circuits is always critical but is particu-
larly important when both analog and digital signals are involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input volt-
age and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch. Ter-
minations for ECL signals should be as close as possible to
the receiving gate.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane on the component
side of the board will reduce noise on the circuit ground. Power
supplies should be capacitively coupled to the ground plane to
reduce noise in the circuit. Multilayer boards allow designers to
lay out signal traces without interrupting the ground plane and
provide low impedance power planes.
It is especially important to maintain the continuity of the ground
plane under and around the AD9060. In systems with dedicated
digital and analog grounds, all grounds of the AD9060 should be
connected to the analog ground plane.
The power supplies (+VS and –VS) of the AD9060 should be
isolated from the supplies used for external devices; this further
reduces the amount of noise coupled into the A/D converter.
Sockets limit the dynamic performance and should be used only
for prototypes or evaluation—PCK Elastomerics Part No. CCS6855
is recommended for the LCC package.
An evaluation board is available to aid designers and provide a
suggested layout.


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