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AD71028 Arkusz danych(PDF) 11 Page - Analog Devices |
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AD71028 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 20 page AD71028 Rev. 0 | Page 11 of 20 PHASE LINEARITY OF THE EXTERNAL ANALOG FILTER If the time alignment of the pilot to the carrier signal is not close to 0 degrees, a loss of separation can occur. This means that the external analog low-pass filter should be a linear-phase design to provide constant group delay over the range from dc to 50 kHz. Bessel filters are recommended for this application. Figure 12 shows a recommended design for these filters. INPUT LEVELS The maximum input level to the AD71028 changes across frequency. Table 10 shows the maximum allowable input level for different frequencies. These values are part of the BTSC specification and are not a function of this chip. Table 10. Maximum Input Levels to the BTSC Encoder across Frequency Frequency (Hz) Maximum Input Level (dBFS) 20 to 1000 0 dB 1600 –1 dB 2500 –3 dB 3150 –5 dB 5000 –8 dB 8000 –11 dB 12500 –15 dB CLOCK RELATIONSHIPS In an MPEG receiver architecture, all clocks are typically generated from a 27 MHz master clock. The following integer relationships are found between the clocks, with Fh = 15.734 kHz: a) 27 MHz/Fh = 1716 = 2 × 2 × 3 × 11 × 13 b) Fh/2 = Fcolor_subcarrier/(5 × 7 × 13) c) 27 MHz/Fcolor_subcarrier = (5 × 7)/(2 × 2 × 2 × 3 × 11) d) 27 MHz/48 kHz = 1125/2 The AD71028 contains a clock doubler circuit that may be used to generate an internal 512 × fS clock when the external clock is 256 × fS. The clock mode is set by connecting the DOUBLE pin either high or low. This pin should be tied either high or low and should not be changed after power-up. The AD71028 requires a master clock at either 256 × 48 kHz (12.288 MHz) when DOUBLE = 1 or 512 × 48 kHz (24.576 MHz) when DOUBLE = 0. In some cases, this signal is provided by the MPEG decoder chip itself. In other cases, only the 27 MHz video clock may be available. In this case, the AD71028 provides on-chip dividers to interface to an external PLL such as the 74HC4046. Figure 4 shows the circuit to accomplish this. The 27 MHz clock is applied to the AD71028 and divided down by 1125, producing a signal at 24 kHz. The PLL oscillator output is divided down by 512, producing a 24 kHz output (when locked). These two signals are applied to the phase-comparator inputs of the external PLL. Note that the divided-down 27 MHz signal looks like a pulse with a duration of one master clock, and therefore only edge-triggered phase detectors should be used. DSP 74HC4046 DIVIDE-BY-1125 DIVIDE-BY-512 27MHz IN AD71028 Figure 4. PLL Connections for 27 MHz Master Clock |
Podobny numer części - AD71028_15 |
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Podobny opis - AD71028_15 |
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