Zakładka z wyszukiwarką danych komponentów |
|
LF2249 Arkusz danych(PDF) 1 Page - LOGIC Devices Incorporated |
|
LF2249 Arkusz danych(HTML) 1 Page - LOGIC Devices Incorporated |
1 / 8 page DEVICES INCORPORATED LF2249 12 x 12-bit Digital Mixer Video Imaging Products 1 2 3 4 5 6 7 8 9 10 11 08/16/2000–LDS.2249-J 1 u u u u u 40 MHz Data and Computation Rate u u u u u Two 12 x 12-bit Multipliers with Individual Data Inputs u u u u u Separate 16-bit Input Port for Cascading Devices u u u u u Independent, User-Selectable 1–16 Clock Pipeline Delay for Each Data Input u u u u u User-Selectable Rounding of Products u u u u u Fully Registered, Pipelined Architecture u u u u u Three-State Outputs u u u u u Fully TTL Compatible u u u u u Replaces TRW/Raytheon/Fairchild TMC2249 u u u u u 120-pin PQFP The LF2249 is a high-speed digital mixer comprised of two 12-bit multipliers and a 24-bit accumulator. All multiplier inputs are user acces- sible, and each can be updated on every clock cycle. The LF2249 utilizes a pipelined architecture with fully registered inputs and outputs and an asynchronous three-state output enable control for optimum flexibility. Independent input register clock enables allow the user to hold the data inputs over multiple clock cycles. Each multiplier input also includes a user-selectable 1-16 clock pipeline delay. The output of each multiplier can be independently negated under NEG1 S15-0 16 RND FT CAS15-0 CASEN SWAP OE 4 4 3 24 16 2 : 1 2 : 1 16 2's COMP 1–16 1–16 ADEL3-0 A11-0 ENA BDEL3-0 B11-0 ENB 2's COMP 1–16 1–16 CDEL3-0 C11-0 ENC DDEL3-0 D11-0 END 4 4 NEG2 ACC CLK NOTE: NUMBERS IN REGISTERS INDICATED NUMBER OF PIPELINE DELAYS. 16 10 0 1 16 MS LS FEATURES DESCRIPTION LF2249 12 x 12-bit Digital Mixer user control for subtraction of prod- ucts. The sum of the products can also be internally rounded to 16 bits during the accumulation process. A separate 16-bit input port con- nected to the accumulator is included to allow cascading of multiple LF2249s. Access to all 24 bits of the accumulator is gained by switching between upper or lower 16-bit words. The accumulated output data is updated on every clock cycle. All inputs and outputs of the LF2249 are registered on the rising edge of clock, except for OE. Internal pipeline registers for all data and control inputs are provided to maintain DEVICES INCORPORATED LF2249 BLOCK DIAGRAM |
Podobny numer części - LF2249 |
|
Podobny opis - LF2249 |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |