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LF2247QC15 Arkusz danych(PDF) 2 Page - LOGIC Devices Incorporated |
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LF2247QC15 Arkusz danych(HTML) 2 Page - LOGIC Devices Incorporated |
2 / 10 page DEVICES INCORPORATED LF2247 Image Filter with Coefficient RAM -2 Video Imaging Products 08/16/2000–LDS.2247-H rising edge of SCLK. The LF2247 operates at a clock rate of 66 MHz over the full temperature and supply voltage ranges. The LF2247 is applicable for perform- ing pixel interpolation in image manipulation and filtering applica- tions. The LF2247 can perform a bilinear interpolation of an image (4- pixel kernels) at real-time video rates when used with an image resampling sequencer. Larger kernels or more complex functions can be realized by utilizing multiple devices. Unrestricted access to all data ports and an addressable coefficient register file provides the LF2247 with consid- erable flexibility in applications such as digital filters, adaptive FIR filters, mixers, and other similar systems requiring high-speed processing. SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clocks CLK — Master Clock The rising edge of CLK strobes all enabled registers except for the coefficient registers. SCLK — Serial Clock The rising edge of SCLK shifts data into and through the coefficient register file when it is enabled for serial data shifting. Inputs D19-0 – D49-0 — Data Input D1–D4 are the 10-bit registered data input ports. Data is latched on the rising edge of CLK. A4-0 — Row Address A4-0 determines which row of data in the coefficient register file is used to feed data to the multiplier array. A4-0 is latched on the rising edge of CLK. When a new row address is loaded into the row address register, data from the register file will be latched into the multiplier input registers on the next rising edge of CLK. SDIN — Serial Data Input SDIN is used to serially load data into the coefficient registers. Data present on SDIN is shifted into the coefficient register file on the rising edge of SCLK when SEN is LOW. The 11-bit coeffi- cients are loaded into the coefficient register file in 16-bit words as shown in Figure 2. The five most significant bits of the first 16-bit word determine which row the data is written to in the coefficient registers. Note that the five most significant bits of the remaining three 16-bit words are ignored. After all four 16-bit words are shifted into the register file, the lower eleven bits of each word (the coefficient data) are stored into the coefficient registers. Outputs S15-0 — Data Output S15-0 is the 16-bit registered data output port. Controls ENB1–ENB4 — Data Input Enables The ENBN (N = 1, 2, 3, or 4) inputs allow the DN registers to be updated on each clock cycle. When ENBN is LOW, data on DN9-0 is latched into FIGURE 1B.OUTPUT FORMATS 15 14 13 10 9 8 12 11 76543210 –2 6 (Sign) 2 5 2 4 2 1 2 0 2 –1 2 3 2 2 2 –2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 15 14 13 10 9 8 12 11 76543210 –2 15 (Sign) 2 14 213 2 10 2 9 2 8 2 12 211 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 Fractional Two's Complement (FSEL = 0) Integer Two's Complement (FSEL = 1) FIGURE 1A.INPUT FORMATS 98 7 2 1 0 –2 0 (Sign) 2 –1 2–2 2 –7 2–8 2–9 10 9 8 2 1 0 –2 1 (Sign) 2 0 2 –1 2 –7 2–8 2–9 98 7 2 1 0 –2 9 (Sign) 2 8 2 7 2 2 2 1 2 0 10 9 8 2 1 0 –2 10 (Sign) 2 9 2 8 2 2 2 1 2 0 Fractional Two's Complement (FSEL = 0) Integer Two's Complement (FSEL = 1) Data Coefficient |
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Podobny opis - LF2247QC15 |
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