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LF2247QC15 Arkusz danych(PDF) 3 Page - LOGIC Devices Incorporated |
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LF2247QC15 Arkusz danych(HTML) 3 Page - LOGIC Devices Incorporated |
3 / 10 page DEVICES INCORPORATED Video Imaging Products 3 LF2247 Image Filter with Coefficient RAM 1 2 3 4 5 6 7 8 9 10 11 08/16/2000–LDS.2247-H the DN register on the rising edge of CLK. When ENBN is HIGH, data on DN9-0 is not latched into the DN register and the register contents will not be changed. ENBA — Row Address Input Enable The ENBA input allows the row address register to be updated on each clock cycle. When ENBA is LOW, data on A4-0 is latched into the row address register on the rising edge of CLK. When ENBA is HIGH, data on A4-0 is not latched into the row address register and the register contents will not be changed. OEN — Output Enable When OEN is LOW, S15-0 is enabled for output. When OEN is HIGH, S15-0 is placed in a high-impedance state. OCEN — Clock Enable When OCEN is LOW, data in the pre- mux register (accumulator output) is loaded into the output register on the next rising edge of CLK. When OCEN is HIGH, data in the pre-mux register is held preventing the output register’s contents from changing (if FSEL does not change). Accumulation continues internally as long as ACC is HIGH, despite the state of OCEN. FSEL — Format Select When FSEL is LOW, the data input during the current clock cycle is assumed to be in fractional two’s complement format, and the upper 16 bits of the accumulator are presented at the output. Rounding of the accumulator result to 16 bits is per- formed if the accumulator control input ACC is LOW. When FSEL is HIGH, the data input is assumed to be in integer two’s complement format, and the lower 16 bits of the accumula- tor are presented at the output. No rounding is performed when FSEL is HIGH. ACC — Accumulator Control The ACC input determines whether internal accumulation is performed on the data input during the current clock cycle. If ACC is LOW, no accumulation is performed, the prior accumulated sum is cleared, and the current sum of products is output. If FSEL is also LOW, one-half LSB rounding to 16 bits is performed on the result. When ACC is HIGH, the emerging product is added to the sum of the previous products, without additional rounding. SEN — Serial Input Enable The SEN input enables the shifting of serial data through the registers in the coefficient register file. When SEN is LOW, serial data on SDIN is shifted into the coefficient register file on the rising edge of SCLK. SEN must remain LOW until all four coefficients have been clocked in. SEN does not need to be pulsed between consecu- tive data sets. It can remain LOW while the entire register file is loaded by a constant bit stream. When SEN is HIGH, data can not be shifted into the register file and the register file’s contents will not be changed. When enabling the coefficient register file for serial data input, the LF2247 requires a HIGH to LOW transition of SEN in order to function properly. Therefore, SEN needs to be set HIGH immedi- ately after power up to ensure proper operation of the serial input circuitry. FIGURE 2. SERIAL DATA FORMAT 23 15 6 48 9 711 12 10 13 15 16 14 18 19 17 21 22 20 24 25 23 27 28 26 29 31 32 30 34 35 33 37 38 36 40 41 39 43 44 42 45 47 48 46 50 51 49 53 54 52 56 57 55 59 60 58 61 63 64 62 00 00 1 11 1 11 0 11 0 0 1X X XX 0 X0 1 00 0 01 0 0 1 XX XX 0 X1 1 01 0 00 0 0 1X X XX 1 X1 1 11 0 10 0 0 1 FIRST 16-BIT WORD SECOND 16-BIT WORD THIRD 16-BIT WORD FOURTH 16-BIT WORD ROW ADDRESS DATA FOR COEFFICIENT REGISTER 4 DON'T CARES DATA FOR COEFFICIENT REGISTER 3 DON'T CARES DATA FOR COEFFICIENT REGISTER 2 DON'T CARES DATA FOR COEFFICIENT REGISTER 1 SHOWN IS SERIAL DATA STREAM TO LOAD ROW ADDRESS 2 WITH: COEFFICIENT REGISTER 1 = 7E4 COEFFICIENT REGISTER 2 = 1A4 COEFFICIENT REGISTER 3 = 08C COEFFICIENT REGISTER 4 = 7EC |
Podobny numer części - LF2247QC15 |
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Podobny opis - LF2247QC15 |
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