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LF2272QC20 Arkusz danych(PDF) 3 Page - LOGIC Devices Incorporated |
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LF2272QC20 Arkusz danych(HTML) 3 Page - LOGIC Devices Incorporated |
3 / 9 page DEVICES INCORPORATED LF2272 Colorspace Converter/ Corrector (3 x 12-bits) 08/16/2000–LDS.2272-I 3 Video Imaging Products SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers. All timing specifi- cations are referenced to the rising edge of CLK. Inputs A11-0, B11-0, C11-0 — Data Inputs A, B, and C are the 12-bit registered data input ports. Data presented to these ports is latched into the multi- plier input registers. KA9-0, KB9-0, KC9-0 — Coefficient Inputs KA, KB, and KC are the 10-bit regis- tered coefficient input ports. Data presented to these ports is latched into the corresponding internal coefficient register set defined by CWEL1-0 (Table 3) on the next rising edge of CLK. Table 2 shows which coefficient registers are available for each coeffi- cient input port. TABLE 2. COEFFICIENT INPUTS INPUT PORT REG. AVAILABLE KA KA1, KA2, KA3 KB KB1, KB2, KB3 KC KC1, KC2, KC3 CWEL1-0 COEFFICIENT SET 00 Hold All Registers 01 KA1, KB1, KC1 10 KA2, KB2, KC2 11 KA3, KB3, KC3 TABLE 3. COEFF. REG. UPDATE Outputs X11-0, Y11-0, Z11-0 — Data Outputs X, Y, and Z are the 12-bit registered data output ports. Controls CWEL1-0 — Coefficient Write Enable The registered coefficient write enable inputs determine which internal coefficient register set to update (Table 3) on the next clock cycle. |
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