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74LV165 Arkusz danych(PDF) 8 Page - NXP Semiconductors |
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74LV165 Arkusz danych(HTML) 8 Page - NXP Semiconductors |
8 / 21 page 74LV165 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 6 — 19 February 2014 8 of 21 NXP Semiconductors 74LV165 8-bit parallel-in/serial-out shift register 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); for test circuit, see Figure 12 Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max tpd propagation delay CE, CP to Q7, Q7; see Figure 7 and Figure 8 [2] VCC = 1.2 V - 115 - - - ns VCC = 2.0 V - 38 61 - 76 ns VCC = 2.7 V - 27 43 - 54 ns VCC = 3.0 V to 3.6 V [3] -22 36 - 45 ns VCC = 3.3 V; CL = 15 pF - 18 - - - ns VCC = 4.5 V to 5.5 V [4] -15 24 - 30 ns PL to Q7, Q7; see Figure 8 VCC = 1.2 V - 110 - - - ns VCC = 2.0 V - 35 56 - 70 ns VCC = 2.7 V - 24 39 - 49 ns VCC = 3.0 V to 3.6 V [3] -20 33 - 41 ns VCC = 3.3 V; CL = 15 pF - 18 - - - ns VCC = 4.5 V to 5.5 V [4] -14 22 - 27 ns D7 to Q7, Q7; CL = 15 pF; see Figure 9 VCC = 1.2 V - 90 - - - ns VCC = 2.0 V - 28 45 - 56 ns VCC = 2.7 V - 20 32 - 40 ns VCC = 3.0 V to 3.6 V [3] -17 27 - 33 ns VCC = 3.3 V; CL = 15 pF - 14 - - - ns VCC = 4.5 V to 5.5 V [4] -11 18 - 22 ns tW pulse width CP input HIGH to LOW; see Figure 7 VCC = 2.0 V 34 10 - 41 - ns VCC = 2.7 V 25 8 - 30 - ns VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns VCC = 4.5 V to 5.5 V [4] 15 5 - 18 - ns PL input LOW; see Figure 8 VCC = 2.0 V 34 10 - 41 - ns VCC = 2.7 V 25 8 - 30 - ns VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns VCC = 4.5 V to 5.5 V [4] 15 5 - 18 - ns |
Podobny numer części - 74LV165_15 |
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Podobny opis - 74LV165_15 |
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