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74LV165 Arkusz danych(PDF) 11 Page - NXP Semiconductors |
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74LV165 Arkusz danych(HTML) 11 Page - NXP Semiconductors |
11 / 21 page 74LV165 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 6 — 19 February 2014 11 of 21 NXP Semiconductors 74LV165 8-bit parallel-in/serial-out shift register Measurement points are given in Table 8. The changing to output assumes that internal Q6 is opposite state from Q7. Fig 8. Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock (CP) and clock enable (CE) recovery time Measurement points are given in Table 8. The changing to output assumes that internal Q6 is opposite state from Q7. Fig 9. Data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW |
Podobny numer części - 74LV165_15 |
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Podobny opis - 74LV165_15 |
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