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74LV595 Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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74LV595 Arkusz danych(HTML) 10 Page - NXP Semiconductors |
10 / 20 page 74LV595_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 21 April 2009 10 of 20 NXP Semiconductors 74LV595 8-bit serial-in/serial-out or parallel-out shift register; 3-state [1] Typical values are measured at Tamb =25 °C. [2] tpd is the same as tPLH and tPHL. [3] Typical value measured at VCC = 3.3 V. [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPHZ and tPLZ. [6] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [7] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(C L × VCC 2 × f o) = sum of outputs. 12. Waveforms fmax maximum frequency SHCP or STCP; see Figure 8 and Figure 9 VCC = 2.0 V 14.0 40.0 - 12 - MHz VCC = 2.7 V 19.0 58.0 - 16 - MHz VCC = 3.3 V; CL = 15 pF - 77 - - - MHz VCC = 3.0 V to 3.6 V [3] 24.0 70.0 - 20 - MHz CPD power dissipation capacitance VI = GND to VCC; VCC = 3.0 V [7] - 115 - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 8. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency mna557 SH CP input Q 7S output tPLH tPHL tW 1/fmax VM VOH VI GND VOL VM |
Podobny numer części - 74LV595_15 |
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Podobny opis - 74LV595_15 |
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