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74LV595 Arkusz danych(PDF) 11 Page - NXP Semiconductors |
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74LV595 Arkusz danych(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 74LV595_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 21 April 2009 11 of 20 NXP Semiconductors 74LV595 8-bit serial-in/serial-out or parallel-out shift register; 3-state Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time mna558 ST CP input Q n output tPLH tPHL tW tsu 1/fmax VM VOH VI GND VOL VM SH CP input VI GND VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The data set-up and hold times for the serial data input (DS) mna560 GND GND th tsu th tsu VM VM VM VI VOH VOL VI Q 7S output SH CP input D S input |
Podobny numer części - 74LV595_15 |
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Podobny opis - 74LV595_15 |
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