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74LV4052 Arkusz danych(PDF) 5 Page - NXP Semiconductors |
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74LV4052 Arkusz danych(HTML) 5 Page - NXP Semiconductors |
5 / 26 page 74LV4052 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 1 July 2013 5 of 26 NXP Semiconductors 74LV4052 Dual 4-channel analog multiplexer/demultiplexer 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values [1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current flows out of terminals nYn. In this case, there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE. [2] The minimum input voltage rating may be exceeded if the input current rating is observed. [3] For DIP16 package: above 70 C the value of P tot derates linearly with 12 mW/K. For SO16 package: above 70 C the value of P tot derates linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 C the value of P tot derates linearly with 5.5 mW/K. Table 3. Function table[1] Input Channel on E S1 S0 LLLnY0 and nZ L L H nY1 and nZ LH LnY2 and nZ L HHnY3 and nZ H X X none Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter Conditions Min Max Unit VCC supply voltage [1] 0.5 +7.0 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [2] - 20 mA ISK switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V [2] - 20 mA ISW switch current VSW > 0.5 V or VSW < VCC + 0.5 V; source or sink current [2] - 25 mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C [3] DIP16 package - 750 mW SO16 package - 500 mW SSOP16 and TSSOP16 package - 400 mW |
Podobny numer części - 74LV4052_15 |
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Podobny opis - 74LV4052_15 |
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