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74LV4094 Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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74LV4094 Arkusz danych(HTML) 10 Page - NXP Semiconductors |
10 / 21 page 74LV4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 19 December 2011 10 of 21 NXP Semiconductors 74LV4094 8-stage shift-and-store bus register [1] All typical values are measured at Tamb = 25 C. [2] All typical values are measured at VCC =3.3 V. [3] tpd is the same as tPLH and tPHL. [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPLZ and tPHZ. [6] tt is the same as tTHL and tTLH. [7] CPD is used to determine the dynamic power dissipation (PD in W). PD =CPD VCC2 fi N+ (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (C L VCC 2 f o) = sum of outputs. 12. Waveforms CPD power dissipation capacitance CL =50pF;f=1 MHz; VI =GND to VCC [7] -83 - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions 40 C to 85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse width and the maximum frequency (CP) 1/fmax tW tPHL tPLH VI GND VOH VOL QPn, QS1 output CP input VM VM 001aaf113 tPHL tPLH VOH VOL QS2 output VM |
Podobny numer części - 74LV4094_15 |
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Podobny opis - 74LV4094_15 |
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