REVISION D 06/16/15

3

15-O/P LP-HCSL DB1900Z DERIVATIVE FOR PCIE GEN1-2-3 AND QPI

9ZXL1550 DATASHEET

Pin Descriptions

PIN #

PIN NAME

TYPE

DESCRIPTION

1

VDDA

PWR

Power for the PLL core.

2

GNDA

GND

Ground pin for the PLL core.

3

100M_133M#

IN

3.3V Input to select operating frequency.

See Functionality Table for Definition

4

HIBW_BYPM_LOBW#

IN

Trilevel input to select High BW, Bypass or Low BW mode.

See PLL Operating Mode Table for Details.

5

CKPWRGD_PD#

IN

3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down

Mode on subsequent assertions. Low enters Power Down Mode.

6

GND

GND

Ground pin.

7

VDDR

PWR

3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and

filtered appropriately.

8

DIF_IN

IN

HCSL True input

9

DIF_IN#

IN

HCSL Complementary Input

10

SMB_A0_tri

IN

SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9

SMBus Addresses.

11

SMBDAT

I/O

Data pin of SMBUS circuitry, 5V tolerant

12

SMBCLK

IN

Clock pin of SMBUS circuitry, 5V tolerant

13

SMB_A1_tri

IN

SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9

SMBus Addresses.

14

FBOUT_NC#

OUT

Complementary half of differential feedback output. This pin should NOT be connected to anything outside

the chip. It exists to provide delay path matching to get 0 propagation delay.

15

FBOUT_NC

OUT

True half of differential feedback output. This pin should NOT be connected to anything outside the chip.

It exists to provide delay path matching to get 0 propagation delay.

16

GND

GND

Ground pin.

17

DIF0

OUT

Differential true clock output

18

DIF0#

OUT

Differential Complementary clock output

19

VDDIO

PWR

Power supply for differential outputs

20

GND

GND

Ground pin.

21

DIF1

OUT

Differential true clock output

22

DIF1#

OUT

Differential Complementary clock output

23

DIF2

OUT

Differential true clock output

24

DIF2#

OUT

Differential Complementary clock output

25

GND

GND

Ground pin.

26

VDD

PWR

Power supply, nominal 3.3V

27

DIF3

OUT

Differential true clock output

28

DIF3#

OUT

Differential Complementary clock output

29

DIF4

OUT

Differential true clock output

30

DIF4#

OUT

Differential Complementary clock output

31

VDDIO

PWR

Power supply for differential outputs

32

GND

GND

Ground pin.