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8V44N4614 Arkusz danych(PDF) 4 Page - Integrated Device Technology |
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8V44N4614 Arkusz danych(HTML) 4 Page - Integrated Device Technology |
4 / 31 page 8V44N4614 DATA SHEET FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER 4 REVISION 1 02/25/15 18 MISO Output Serial Control Port SPI Mode Data Output. 1.8V LVCMOS (JESD8-7A) output levels. 19 VDDOB Power Supply voltage for the QB bank clock outputs (3.3V). 20 QB3 Output Single-ended clock output B3. Complementary to QB2 when configured as inverted output. 3.3V LVCMOS/LVTTL output levels. 21 QB2 Output Single-ended clock output B2. 3.3V LVCMOS/LVTTL output levels. 22 QB1 Output Single-ended clock output B1. Complementary to QB0 when configured as inverted output. 3.3V LVCMOS/LVTTL output levels. 23 QB0 Output Single-ended clock output B0. 3.3V LVCMOS/LVTTL output levels. 25 OENB Input Pulldown Output enable (active high). 3.3V LVCMOS/LVTTL interface levels. See Table 3J for function. 26 DNU – Do not connect and do not use. 27 OENA Input Pullup Output enable (active high). 3.3V LVCMOS/LVTTL interface levels. See Table 3J for function. 28, 34 VDDOC Power Supply voltage for the QC bank clock outputs (3.3V) 30 QC3 Output Single-ended clock output C3. Complementary to QC2 when configured as inverted output. 3.3V LVCMOS/LVTTL output levels. 31 QC2 Output Single-ended clock output C2. 3.3V LVCMOS/LVTTL output levels. 32 QC1 Output Single-ended clock output C1. Complementary to QC0 when configured as inverted output. 3.3V LVCMOS/LVTTL output levels. 33 QC0 Output Single-ended clock output C0. 3.3V LVCMOS/LVTTL output levels. 36 TEST Input Pulldown Test mode control input. Compatible with LVCMOS/LVTTL (3.3V) signals. See Table 3C for function. 39 BYPASS Input Pulldown PLL Bypass control input. Compatible with LVCMOS/LVTTL (3.3V) signals. See Table 3B for function. 41 VDDA Power Supply voltage for the internal PLL (3.3V) 42 LOCK Output PLL lock detect output. 3.3V LVCMOS/LVTTL output levels. 44 nCLK Input Pullup / Pulldown Inverting differential clock input. Inverting input is biased to VDD / 2 by default when left floating. Compatible with LVPECL and LVDS signals. 45 CLK Input Pulldown Non-inverting differential input clock. Compatible with LVPECL and LVDS signals. 46 VDDI Power Core voltage for the reference clock (input) circuits (3.3V) 47 LCLK Input Pulldown Alternative clock input. Compatible with LVCMOS/LVTTL (3.3V) signals. 48 REFSEL Input Pulldown PLL reference select control input. Compatible with LVCMOS/LVTTL (3.3V) signals.See Table 3A for function. – VEE_EP Power Exposed pad of package. Connect to GND. Table 1: Pin Descriptions (Continued) Number Name Type Description |
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