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93LCS66-IP Arkusz danych(PDF) 5 Page - Microchip Technology |
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93LCS66-IP Arkusz danych(HTML) 5 Page - Microchip Technology |
5 / 12 page © 1996 Microchip Technology Inc. Preliminary DS11181D-page 5 93LCS56/66 The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns (TCSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruc- tion. WRITE instruction is valid only if specified address is unprotected. The WRITE cycle takes 4 ms per word typical. 2.8 Erase All (ERAL) The ERAL instruction will erase the entire memory array to the logical “1”. The ERAL cycle is identical to the ERASE cycle except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. PE pin MUST be held “high” while loading the instruction but becomes “don't care” thereafter. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is guaranteed at VCC = 4.5 to 6V and valid only when Protect Register is cleared. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. The ERAL cycle takes 15 ms maximum (8 ms typical). 2.9 Write All (WRAL) The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. PE pin MUST be held “high” while loading the instruction but becomes “don't care” thereafter. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is guar- anteed at VCC = 4.5 to 6V and valid only when Protect Register is cleared. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). The WRAL cycle takes 30 ms maximum (16 ms typical). Note: In order to execute either READ, EWEN, ERAL, WRITE, WRAL, or EWDS instruc- tions, the Protect Register Enable (PRE) pin must be held LOW. 2.10 Protect Register Read (PRREAD) The Protect Register Read (PRREAD) instruction out- puts the address stored in the Protect Register on the DO pin. The PRE pin MUST be held HIGH when load- ing the instruction and remains HIGH until CS goes LOW. A dummy zero bit precedes the 8-bit output string. The output data bits in the memory Protect Reg- ister will toggle on the rising edge of the CLK as in the READ mode. 2.11 Protect Register Enable (PREN) The Protect Register Enable (PREN) instruction is used to enable the PRCLEAR, PRWRITE, and PRDS modes. Before the PREN mode can be entered, the device must be in the EWEN mode. Both PRE and PE pins MUST be held “high” while loading the instruction. The PREN instruction MUST immediately precede a PRCLEAR, PRWRITE, or PRDS instruction. 2.12 Protect Register Clear (PRCLEAR) The Protect Register Clear (PRCLEAR) instruction clears the address stored in the Protect Register and, therefore, enables all registers for programming instructions such as ERASE, ERAL, WRITE, and WRAL. The PRE and PE pin MUST be held HIGH when loading the instruction. Thereafter, PRE and PE pins become “don't care”. A PREN instruction must immedi- ately precede a PRCLEAR instruction. 2.13 Protect Register Write (PRWRITE) The Protect Register Write (PRWRITE) instruction writes into the Protect Register the address of the first register to be protected. After this instruction is exe- cuted, all registers whose memory addresses are greater than or equal to the address pointer specified in the Protect register are protected from any program- ming instructions. Note that a PREN instruction must be executed before a PRWRITE instruction and, the Protect Register must be cleared (by a PRCLEAR instruction) before executing the PRWRITE instruction. The PRE and PE pins MUST be held HIGH while load- ing PRWRITE instruction. After the instruction is loaded, they become “don't care”. 2.14 Protect Register Disable (PRDS) The Protect Register Disable (PRDS) instruction is a ONE TIME ONLY instruction to permanently set the address specified in the Protect Register. Any attempts to change the address pointer will be aborted. The PRE and PE pins MUST be held HIGH while loading PRDS instruction. After the instruction is loaded, they become “don't care”. Note that a PREN instruction must be exe- cuted before a PRDS instruction. |
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